MAX1247 4-Channel, 12-Bit ADC

[mister_e]

First observation, you have to disable ADCs on PORTA
ADCON1=7

and at the top, you should insert a short PAUSE (let's say 50) after
CSpin = 1
Just for safety sake


sorry i'm too lazy tonight to check the whole thing

Fortunately, someone else may have a deeper look to?

[Atom058]

Steve - I was really hoping that the ADCON1 thing was it as I missed that one, but still no go. I did the 50 mS pause you recommended, too.

I can't help but think this is one of those "can't see the forest through the trees" thing. I'm sure it's staring me right in the face. I am using a 12 bit D/A (4-channel) chip (MAX525) on this board as well and it works perfectly. Can't imagine why the A/D chip is giving me such a hard time...

Let me know if you think of anything else! Thanks!

[Atom058]

This is out of the data sheet for the MAX1247:

"the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit transfers
to clock out the 12-bit conversion result)."

"Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull CS low.

3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3.

6) Pull CS high.

Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock frequency
and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120μs."

This seems to be telling me that I have to shift out 3 bytes (control, $00, $00) and I read back 3 bytes - the result is contained in the 2nd two bytes. It also mentions choosing a clock frequency of 100kHz to 2MHz. How do I do that?

I made a stab at the three out, three in routine but no result:

ReadADC:
low CSpin
shiftout doutpin, clkpin, 1, [cb] 'Send Control Byte
shiftin dinpin, clkpin, 0, [rb1] 'Read RB1 in and discard
shiftout doutpin, clkpin, 1, [$00] 'Send a byte of zeros
shiftin dinpin, clkpin, 0, [rb2] 'Read RB2
shiftout doutpin, clkpin, 1, [$00] 'Send a byte of zeros
shiftin dinpin, clkpin, 0, [rb3] 'Read RB3 - RB2&3 contain result
high cspin

return

Am I using the right modes for shiftin and out?