Ok I see your point, although those aren't quite equivalent yet. A verilog statement like Datum[6:4] = 2 would change all bits from bit 6 to bit 4 of Datum, turning Datum into X010XXXX where the X's are the previous bit values of Datum before the statement. So referring to Datum as Datum[6:4] is like having a new 3 bit variable where Datum[4] is the new bit 0, Datum[5] is the new bit 1 and Datum[6] is the new bit 2 to complete the three bit variable. But thanks I guess I'll have to work my way around with those sort of tricks. Thanks for your time, God bless.