Here's a possibility...

When you disable the SSP module, the pin goes to the state that it was last set to, independant of where the SSP left it.

After sending the ninth bit, it leaves sclk at 1. So the next time you disable the SSP the SCK pin will go back to 1 and clock in a "bad" bit. The rest of the bits will then be offset by one position.

Make sure to set the pin to the correct state before disabling the SSP.