Success!!!

First, I tried deleting the whole "else" section with the delays. My circuit worked
OK, but the active pulse width was less than 400ns. Too short for me to feel
comfortable about reliability. So then I tried changing all the "2"s to "1"s in the
"else" section. I got errors when I compiled. So, I deleted the "if" statements
for the lower speed oscillators and it looks pretty good now. I still wish it was
faster, but speeding it up seems to shrink the active pulse width too much.

For reference:

No delays (removing all the "else" statements): 3.6us clock (278kHz)
No delays up to 16MHz: 4us clock (250kHz)

Here is what I have:

ifdef SHIFTTOGGLE_USED
LIST
shifttoggle
movf RM2, W ; Get clock bit mask
xorwf INDF1, F ; Toggle clock
ifdef SHIFT_PAUSEUS
movf R0, W ; Save shift data
movwf R1
movf R0 + 1, W
movwf R1 + 1
movlw (SHIFT_PAUSEUS) >> 8 ; Slow down transfer
movwf R0 + 1
movlw low (SHIFT_PAUSEUS)
call PAUSEUSL
movf R1, W ; Restore shift data
movwf R0
movf R1 + 1, W
movwf R0 + 1
movf RM2, W ; Get clock bit mask
PAUSEUS_USED = 1
else
nop ; Slow down transfer
if (OSC > 16)
bra $ + 2
endif
if (OSC > 20)
bra $ + 2
endif
if (OSC > 25)
bra $ + 2
bra $ + 2
endif
if (OSC > 33)
bra $ + 2
bra $ + 2
endif
if (OSC > 40)
bra $ + 2
endif
endif
xorwf INDF1, F
return
NOLIST
endif