Brock,
I am curious about this as I plan on using this feature, but have not gotten to that point in my project yet. The manual is a bit vague in it's statement "The shift clock runs at about 50KHz dependent on the oscillator". Have you tested the actual speed?

Here's why I ask. Looking at the ASM produced by PBP, the SHIFTIN/SHIFTOUT seem to control the speed of the clock using the same subroutine ("shifttoggle"). This routine adds dummy BRA calls based on the defined OSC. If I've counted correctly the "shifttoggle" routine takes 6 instructions cycles for OCS 4MHz (6us), and 24 instructions cycles for 40MHz (2.4us). There are about 14 or so additional instructions in the SHIFTOUT routine. So for 4MHz, 20 total instruction cycles (20us) would result in around 50kHz. But, at 40MHz, 38 instruction cycles (3.8us) would be about 263KHz. Which leads me to believe that at faster OSC, the actual frequency of the clock would be faster (otherwise I would have expected the routine to have 60 instruction cycles for 40MHz OSC). I may have missed something, but don't have the time to actually check it out and measure it on a scope at this time.

I'm already using the MSSP for I2C and, like you, would have to change my design to accomadate using the MSSP for SPI.

Curiously,
Steve