Thanks for the reply. The data sheets do not indicates that any of the ports I am using are open drain:

On the 16f676 (master):
* portc.1 for Tx - RC1/AN5
* portc.2 for Rx - RC2/AN5

On the 12F675 (slave):
* gpio 4 for Tx - GP4/AN3/T1G/OSC2/CLKOUT
* gpio 2 for Rx - GP2/AN2/T0CKI/INT/COUT


I did have one problem: I did not have ANSEL and CMCON set correctly for the master - setting this correctly solved the second problem about the master not triggering off the WAIT on SERIN2.

But I still have the problem between the Tx (portc.1) on the master, and the Rx (gpio 2) on the slave - it only works with the Logic analyzer OR scope connected.

The signal under the scope goes from rail to rail (0v to +5v), however, I notice that after the last signal, there is not a straight drop off, but an inverse drop 1ms in length, like a capacitor draining?? I only have an analog scope, so this is a fleeting signal. I try this on other data lines, and I do not see the curve.

Also note: that on the 12F675 slave, I have external interupts enabled on the GP2 pin. I do not have a handler, I use it only to see if data has come in on the Rx pin.

Suggestions of where I should look?

thanks
Don