So I have checked all registers concerning the Ports and Timers source clocks. Add them to my program.
Here is the setup:


DEFINE OSC 4
DEFINE CHAR_PACING 2000
INCLUDE "modedefs.bas"


#CONFIG
CONFIG FEXTOSC = HS ;HS (crystal oscillator) above 8 MHz; PFM set to high power
CONFIG RSTOSC = EXTOSC ;EXTOSC operating per FEXTOSC bits (device manufacturing default)
CONFIG CLKOUTEN = OFF ;CLKOUT function is disabled
CONFIG CSWEN = ON ;Writing to NOSC and NDIV is allowed
CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
CONFIG MCLRE = EXTMCLR ;MCLR pin (RE3) is MCLR
CONFIG PWRTE = ON ;Power up timer enabled
CONFIG LPBOREN = OFF ;Low power BOR is disabled
CONFIG BOREN = ON ;Brown-out Reset enabled according to SBOREN
CONFIG BORV = VBOR_245 ;Brown-out Reset Voltage (VBOR) set to 2.45V
CONFIG ZCD = OFF ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
CONFIG PPS1WAY = OFF ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
CONFIG STVREN = ON ;Stack full/underflow will cause Reset
CONFIG XINST = OFF ;Extended Instruction Set and Indexed Addressing Mode disabled
CONFIG WDTCPS = WDTCPS_31 ;Divider ratio 1:65536; software control of WDTPS
CONFIG WDTE = SWDTEN ;WDT enabled/disabled by SWDTEN bit
CONFIG WDTCWS = WDTCWS_7 ;window always open (100%); software control; keyed access not required
CONFIG WDTCCS = SC ;Software Control
CONFIG WRT0 = OFF ;Block 0 (000800-001FFFh) not write-protected
CONFIG WRT1 = OFF ;Block 1 (002000-003FFFh) not write-protected
CONFIG WRTC = OFF ;Configuration registers (300000-30000Bh) not write-protected
CONFIG WRTB = OFF ;Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ;Data EEPROM not write-protected
CONFIG SCANE = ON ;Scanner module is available for use, SCANMD bit can control the module
CONFIG LVP = OFF ;HV on MCLR/VPP must be used for programming
CONFIG CP = OFF ;UserNVM code protection disabled
CONFIG CPD = OFF ;DataNVM code protection disabled
CONFIG EBTR0 = OFF ;Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ;Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG


data @0,0 'Mode tête et pied inversé Rotec
data @1,1 'afficheur 6r pre-compile
data @2,0 'th12 (Permobil et Span) pre-compile relais
data @3,0 'Linak hl70d (Euro) pre-compile
data @4,0 'TC1 (Permobil et Span serial) pre-compile pas fait
data @5,0 'TC14 (Sotec serial) pre-compile
data @6,0 'Umano pre-compile
data @7,0 'Permobil Trost pre-compile
data @8,1 'Permobil Noa TC1 relais pre-compile (Comme Span mais différents boutons/fonctions)
data @9,0 'Bertek 9 pins pre-compile


'************************************************* ***
' Initialisation des modules internes 18F46Q10 *
'************************************************* ***


'Analog to digital converters
ANSELA = 0
ANSELB = 0
ANSELD = 0
ANSELE = 0


'Open Drain (NO)
ODCONA = 0
ODCONB = 0
ODCONC = 0
ODCOND = 0
ODCONE = 0


'Slew rate
SLRCONA = 0
SLRCONB = 0
SLRCONC = 0
SLRCOND = 0
SLRCONE = 0


'Input threshold (TTL)
INLVLA = 0
INLVLB = 0
INLVLC = 0
INLVLD = 0
INLVLE = 0


'Weak Pull-Up
WPUA = 0
WPUB = 0
WPUC = 0
WPUD = 0
WPUE = 0


'Timers
T0CON1 = %01000000 'source Fosc/4
T1CLK = %00000001 'source Fosc/4
T2CLKCON = %00000001 'source Fosc/4
T3CLK = %00000001 'source Fosc/4
T4CLKCON = %00000001 'source Fosc/4
T5CLK = %00000001 'source Fosc/4
T6CLKCON = %00000001 'source Fosc/4


It changed nothing. I always put a blinking led and a "beep" on startup. So I switched my PIEZO for the LED (PORTD.0). So I can see the LED "SOUND"


sound led_1,[124,20]


The led should be ON for about 20x12ms so 240ms. It's ON for exactly 240ms and the period is 400us (2.5Khz) All Ok here. So I "Input' my Piezo pin, place a jumper from my led (removed and 1k res removed) to the piezo. No drive, no PWM, just HIGH and then LOW after 240ms. I must be doing something wrong. I don't know.


The second thing not working is the SERIN function. All rejected after timeout. I did not investigate this one yet.