16F18446 - maybe missing some registers settings
Since I don't use MPLAB but "only" the MPASM Suite, I don't have this folder.check in the configuration INC file in the mpasmx folder.
Instead, I found the 1F18446.INFO file in the PBP3 folder which provides CONFIG settings:
Strangely, some CONFIG2 default settings are not listed in this .INFO file ?! What is right, what is wrong or why is it so? Does it affect my circuit?Code:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; File: PIC16F18446.INFO ; Date: 02/01/20 ; Generated by melabs File Manager ; ; PICBASIC PRO(tm) Compiler version: 3.1.3 ; ; Copyright 2020 ME Labs, Inc. All Rights Reserved ; The content herein is intended to facilitate embedded development using ; PICBASIC PRO Compiler. Reproduction or utilization for other purposes ; is prohibited without written permission from ME Labs, Inc.. ; ; ME Labs, Inc. ; PO Box 8250 ; Asheville NC 28814 ; 719-520-5323 ; fax: 719-520-1867 ; http://melabs.com ; [email protected] ; ; Modifications to this file in the \DEVICE_REFERENCE folder will be ; overwritten when you install future upgrades. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;MPASM __CONFIG Directive Options ; ; The PBP default configuration for the PIC16F18446 is: ; ; #CONFIG ; __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON ; __config _CONFIG2, _MCLRE_ON & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_SBOREN & _BORV_LO & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_ON ; __config _CONFIG3, _WDTCPS_WDTCPS_31 & _WDTE_SWDTEN & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC ; __config _CONFIG4, _BBSIZE_BB512 & _BBEN_OFF & _SAFEN_OFF & _WRTAPP_OFF & _WRTB_OFF & _WRTC_OFF & _WRTD_OFF & _WRTSAF_OFF & _LVP_OFF ; __config _CONFIG5, _CP_OFF ; #ENDCONFIG ; ; You may use the information below to construct your own configuration ; directives for the PIC16F18446. Please note that ALL DEFAULT ; CONFIGURATION SETTINGS WILL BE OVERWRITTEN when you include a #CONFIG ; block in your program. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Available __CONFIG labels for PIC16F18446: ; ;CONFIG1 Options ; ; External Oscillator mode selection bits ; _FEXTOSC_ECH ;EC above 8MHz; PFM set to high power ; _FEXTOSC_ECM ;EC for 500kHz to 8MHz; PFM set to medium power ; _FEXTOSC_ECL ;EC below 500kHz; PFM set to low power ; _FEXTOSC_OFF ;Oscillator not enabled ; _FEXTOSC_RESERVED ;Reserved ; _FEXTOSC_HS ;HS (crystal oscillator) above 4MHz; PFM set to high power ; _FEXTOSC_XT ;XT (crystal oscillator) above 500kHz, below 4MHz; PFM set to medium power ; _FEXTOSC_LP ;LP (crystal oscillator) optimized for 32.768kHz; PFM set to low power ; ; Power-up default value for COSC bits ; _RSTOSC_EXT1X ;EXTOSC operating per FEXTOSC bits ; _RSTOSC_HFINT1 ;HFINTOSC (1MHz) ; _RSTOSC_LFINT ;LFINTOSC ; _RSTOSC_SOSC ;SOSC ; _RSTOSC_RESERVED ;Reserved ; _RSTOSC_EXT4X ;EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits ; _RSTOSC_HFINTPLL ;HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1 (FOSC = 32 MHz) ; _RSTOSC_HFINT32 ;HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1 ; ; Clock Out Enable bit ; _CLKOUTEN_ON ;CLKOUT function is enabled; FOSC/4 clock appears at OSC2 ; _CLKOUTEN_OFF ;CLKOUT function is disabled; i/o or oscillator function on OSC2 ; ; Clock Switch Enable bit ; _CSWEN_ON ;Writing to NOSC and NDIV is allowed ; _CSWEN_OFF ;The NOSC and NDIV bits cannot be changed by user software ; ; Fail-Safe Clock Monitor Enable bit ; _FCMEN_ON ;FSCM timer enabled ; _FCMEN_OFF ;FSCM timer disabled ; ;CONFIG2 Options ; ; Master Clear Enable bit ; _MCLRE_ON ;MCLR pin is Master Clear function ; _MCLRE_OFF ;MCLR pin function is port defined function ; ; Power-up Timer Enable bit ; _PWRTS_OFF ;PWRT disabled ; _PWRTS_PWRT_64 ;PWRT set at 64 ms ; _PWRTS_PWRT_16 ;PWRT set at 16 ms ; _PWRTS_PWRT_1 ;PWRT set at 1 ms ; ; Low-Power BOR enable bit ; _LPBOREN_OFF ;ULPBOR disabled ; _LPBOREN_ON ;ULPBOR enabled ; ; Brown-out reset enable bits ; _BOREN_ON ;Brown-out Reset Enabled, SBOREN bit is ignored ; _BOREN_NSLEEP ;Brown-out Reset enabled while running, disabled in sleep; SBOREN is ignored ; _BOREN_SBOREN ;Brown-out reset enabled according to SBOREN bit ; _BOREN_OFF ;Brown-out reset disabled ; ; Brown-out Reset Voltage Selection ; _BORV_LO ;Brown-out Reset Voltage (VBOR) set to 2.45V ; _BORV_HI ;Brown-out Reset Voltage (VBOR) is set to 2.7V ; ; Zero-cross detect disable ; _ZCD_OFF ;Zero-cross detect circuit is disabled at POR. ; _ZCD_ON ;Zero-cross detect circuit is always enabled ; ; Peripheral Pin Select one-way control ; _PPS1WAY_ON ;The PPSLOCK bit can be cleared and set only once in software ; _PPS1WAY_OFF ;The PPSLOCK bit can be set and cleared repeatedly by software ; ; Stack Overflow/Underflow Reset Enable bit ; _STVREN_ON ;Stack Overflow or Underflow will cause a reset ; _STVREN_OFF ;Stack Overflow or Underflow will not cause a reset ; ;CONFIG3 Options ; ; WDT Period Select bits ; _WDTCPS_WDTCPS_0 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_1 ;Divider ratio 1:64 ; _WDTCPS_WDTCPS_2 ;Divider ratio 1:128 ; _WDTCPS_WDTCPS_3 ;Divider ratio 1:256 ; _WDTCPS_WDTCPS_4 ;Divider ratio 1:512 ; _WDTCPS_WDTCPS_5 ;Divider ratio 1:1024 ; _WDTCPS_WDTCPS_6 ;Divider ratio 1:2048 ; _WDTCPS_WDTCPS_7 ;Divider ratio 1:4096 ; _WDTCPS_WDTCPS_8 ;Divider ratio 1:8192 ; _WDTCPS_WDTCPS_9 ;Divider ratio 1:16384 ; _WDTCPS_WDTCPS_10 ;Divider ratio 1:32768 ; _WDTCPS_WDTCPS_11 ;Divider ratio 1:65536 ; _WDTCPS_WDTCPS_12 ;Divider ratio 1:131072 ; _WDTCPS_WDTCPS_13 ;Divider ratio 1:262144 ; _WDTCPS_WDTCPS_14 ;Divider ratio 1:524299 ; _WDTCPS_WDTCPS_15 ;Divider ratio 1:1048576 ; _WDTCPS_WDTCPS_16 ;Divider ratio 1:2097152 ; _WDTCPS_WDTCPS_17 ;Divider ratio 1:4194304 ; _WDTCPS_WDTCPS_18 ;Divider ratio 1:8388608 ; _WDTCPS_WDTCPS_19 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_20 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_21 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_22 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_23 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_24 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_25 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_26 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_27 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_28 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_29 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_30 ;Divider ratio 1:32 ; _WDTCPS_WDTCPS_31 ;Divider ratio 1:65536; software control of WDTPS ; ; WDT operating mode ; _WDTE_OFF ;WDT Disabled, SWDTEN is ignored ; _WDTE_SWDTEN ;WDT enabled/disabled by SWDTEN bit in WDTCON0 ; _WDTE_NSLEEP ;WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored ; _WDTE_ON ;WDT enabled regardless of sleep; SWDTEN ignored ; ; WDT Window Select bits ; _WDTCWS_WDTCWS_0 ;window delay = 87.5 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_1 ;window delay = 75 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_2 ;window delay = 62.5 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_3 ;window delay = 50 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_4 ;window delay = 37.5 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_5 ;window delay = 25 percent of time; no software control; keyed access required ; _WDTCWS_WDTCWS_6 ;window always open (100%); no software control; keyed access required ; _WDTCWS_WDTCWS_7 ;window always open (100%); software control; keyed access not required ; ; WDT input clock selector ; _WDTCCS_LFINTOSC ;WDT reference clock is the 31.0kHz LFINTOSC output ; _WDTCCS_HFINTOSC ;WDT reference clock is the 31.25 kHz HFINTOSC ; _WDTCCS_SOSC ;WDT reference clock is the 32kHz secondary oscillator ; _WDTCCS_SC ;Software Control ; ;CONFIG4 Options ; ; Boot Block Size Selection bits ; _BBSIZE_BB512 ;512 words boot block size ; _BBSIZE_BB1K ;1024 words boot block size ; _BBSIZE_BB2K ;2048 words boot block size ; _BBSIZE_BB4K ;4096 words boot block size ; _BBSIZE_BB8K ;8192 words boot block size ; _BBSIZE_BB16K ;* half of user program memory ; _BBSIZE_BB32K ;* half of user program memory ; _BBSIZE_BB64K ;* half of user program memory ; ; Boot Block Enable bit ; _BBEN_OFF ;Boot Block disabled ; _BBEN_ON ;Boot Block enabled ; ; SAF Enable bit ; _SAFEN_OFF ;SAF disabled ; _SAFEN_ON ;SAF enabled ; ; Application Block Write Protection bit ; _WRTAPP_OFF ;Application Block not write protected ; _WRTAPP_ON ;Application Block write protected ; ; Boot Block Write Protection bit ; _WRTB_OFF ;Boot Block not write protected ; _WRTB_ON ;Boot Block write protected ; ; Configuration Register Write Protection bit ; _WRTC_OFF ;Configuration Register not write protected ; _WRTC_ON ;Configuration Register write protected ; ; Data EEPROM write protection bit ; _WRTD_OFF ;Data EEPROM NOT write protected ; _WRTD_ON ;Data EEPROM write protected ; ; Storage Area Flash Write Protection bit ; _WRTSAF_OFF ;SAF not write protected ; _WRTSAF_ON ;SAF write protected ; ; Low Voltage Programming Enable bit ; _LVP_ON ;Low Voltage programming enabled. MCLR/Vpp pin function is MCLR. ; _LVP_OFF ;High Voltage on MCLR/Vpp must be used for programming ; ;CONFIG5 Options ; ; UserNVM Program memory code protection bit ; _CP_OFF ;UserNVM code protection disabled ; _CP_ON ;UserNVM code protection enabled ; ; ;/MPASM ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Anyway, for a try, I modified my CONFIG2 line like:
__config _CONFIG2, _MCLRE_OFF & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_OFF & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF
instead of:
__config _CONFIG2, _MCLRE_OFF & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_OFF & _BORV_LO & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_ON
Still not even a flicker on my display...and I corrected from LATx to PORTx.
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