Pic18f67k22 WDT

[richard]

a simple example to demonstrate WDT

'****************************************************************'*  Name    : UNTITLED.BAS                                      *
'*  Author  : richard                                           *
'*  Notice  : Copyright (c) 2024 caveat emptor                  *
'*          : All Rights Reserved                               *
'*  Date    : 17/11/2024                                        *
'*  Version : 1.0                                               *
'*  Notes   :                                                   *
'*          :                                                   *
'****************************************************************
#config
 CONFIG RETEN=OFF
 CONFIG XINST = OFF ;Extended Instruction Set
 CONFIG FOSC = INTIO2 ;internal RC oscillator
 
 CONFIG SOSCSEL=DIG


 CONFIG FCMEN = OFF   ;Fail-Safe Clock Monitor ****
 CONFIG IESO = OFF  ;Two-Speed Start-up is disabled
 CONFIG PLLCFG = OFF  ;4x xtal PLL


 
 CONFIG PWRTEN = ON ;Power-up Timer
 CONFIG BOREN = SBORDIS ; Brown-out Reset Enabled in hardware, SBOREN disabled
 CONFIG BORPWR = HIGH ;BOR MV set to high power level
 CONFIG BORV = 2 ; Brown-out Reset  0=3v, 1=2.7v, 2=2v, 3=1.8v
 
 CONFIG WDTEN = SWDTDIS ;ON ;OFF ;WDT enabled in hardware; SWDTEN bit disabled
 CONFIG WDTPS = 512 ;WDT     512*4Ms = 2 SECONDS
 
 CONFIG RTCOSC = INTOSCREF  ; RTCC uses INTRC


 
 CONFIG  MCLRE = ON


 CONFIG STVREN = ON ;Stack Full/Underflow Reset


 CONFIG DEBUG = OFF ;Background Debugger
 
 CONFIG CP0 = ON  ;code-protected
 CONFIG CP1 = ON
 CONFIG CP2 = ON
 CONFIG CP3 = ON
 CONFIG CP4 = ON
 CONFIG CP5 = ON
 CONFIG CP6 = ON
 CONFIG CP7 = ON
 CONFIG CPB = ON  ;Boot Block Code Protection
 CONFIG CPD = ON  ;Data EEPROM Code Protection 


#endconfig


DEFINE NO_CLRWDT 1 'Don’t insert CLRWDTs 


DEFINE DEBUG_REG PORTD         
DEFINE DEBUG_BIT 4
DEFINE DEBUG_BAUD 9600 
DEFINE DEBUG_MODE 0  '0=TRUE 1=INVERTER


'*** At 64MHz each instruction cycle is 62.5ns 
    OSCCON=%11110100 'OSCILLATOR CONTROL & Frequency  (16M RC)
    OSCTUNE.6=1 'Frequency Multiplier PLL Enable bit FOR INIT RC


DEFINE OSC 64 
    TRISD=$ed
    ANCON0=0 'AN0-AN7 digital port
    ANCON1=0 'AN8-AN15 digital port
    ANCON2=0 'AN16-AN23 dig
    CM1CON.7=0 'COMPERATOR1 OFF
    CM2CON.7=0 'COMPERATOR2 OFF
    CM3CON.7=0 'COMPERATOR3 OFF


    PSPCON.4=0 'General Purpose I/O mode 'PSPMODE: Parallel Slave Port Mode Select bit
    
    latd=18
    @ CLRWDT        ;WDT needs to be cleared every   512*4Ms = 2 SECONDS  at most else chip will reset
 
    pause 100
    @ CLRWDT
    debug "ready",13,10
    @ CLRWDT
    MAIN:              ; if porta.0 is not detected going high the wdt will overflow and reset chip     
        LATD.1=0
        IF PORTA.0 THEN 
            @ CLRWDT       ; in main loop the wdt is cleared when porta.0 goes high 
            WHILE PORTA.0 : WEND         
        ENDIF  
    GOTO MAIN  
 




stop

[amgen]

************************************************** **************'* Name : UNTITLED.BAS *
'* Author : richard *
'* Notice : Copyright (c) 2024 caveat emptor *
'* : All Rights Reserved *
'* Date : 17/11/2024 *
'* Version : 1.0 *
'* Notes : *
'* : *
'************************************************* ***************
#config
CONFIG RETEN=OFF
CONFIG XINST = OFF ;Extended Instruction Set

Are you a wizard of some kind.......... you wrote/posted this a day ahead of today...... writing now in the future ??????

warning: I am an idiot!

[richard]

you wrote/posted this a day ahead of today

the world is not flat , time is relative

[eyalbiton]

Hello Richard

Thanks a lot for the help.