Re: SOLVED: How can I reduce ADC drift
But the readings will have a play around the specific point
agreed , at the 1/4 turn posn the raw reading expected WHEN vref == vdd and vdd is a well filtered stable supply would be 256 + or - 1 count. if you want better than that use either a 12 bit adc or averaging or oversampling. none of which come without a cost.
This all becomes a ridiculous overkill if the "pot" for instance represents say the 'CHOKE' position when it is displayed as 0-100 in 5% steps.
i have asked several times now what are your expectations ?
Warning I'm not a teacher
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