Re: SOLVED: How can I reduce ADC drift
to measure ac noise on rail , noise hopefully in mV and not to many of them
for any dc , logic measurements
1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.
raw adc will never have no jitter
2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.
the word you want here is resolution, if you had a 1k pot and 10 bit adc you could resolve it to 1 ohm steps in theory
but adc is always has +- count , jitter free might get to 255 steps, you need to design for the outcome desired
3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.
depending on noise and needed resolution there are ways , from simple division, averaging or oversampling
4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.
its not designed to average more than one ch and need exclusive use of the adc but have a go
Warning I'm not a teacher
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