SOLVED: How can I reduce ADC jitter

[richard]

- did not touch VREFs,
What do you mean by this , you have changes pos vref to fvr buffer1- used FVR 4x with 5 VDC in,
which will turn out to be a mistake since pots use vdd as top input , by doing this you have lost 20% of their travel range




Anything over VREF+ will be interpreted as the max ADC output. Anything lower than VREF- will be interpreted as the min ADC output value.
There will be no damage if you exceed VREF+/VREF- as long as you don't exceed Vdd/Vss

- used FOSC / 128,way too slow , while not out of acceptable range fosc/32 is more reasonable
- used average of 16 ADC readings,not sure about that , its not necessary either if every thing else is ok


- used USART to show results
- added PAUSEUS 1 after all ADC operations - THIS NEEDS TO BE VERIFIED IF IT'S NECESSARY, it was just to make sure things worked.
it does nothing useful


my schema , added another supply rail straddling 10k pot , without series wiper resistor to an2
not no none nil caps across an inputs



typical raw readings

R 827    669
R 826    669
R 826    669
R 826    668
R 825    669
R 827    669
R 826    669
R 826    669
R 826    668
R 825    668
R 827    670
R 826    669
R 825    668
R 827    669
R 827    669

#CONFIG
__config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
__config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
__config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
__config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON
__config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG


DEFINE OSC 32

DEFINE DEBUG_REG PORTC
DEFINE DEBUG_BIT 0 ; if not used for pwr
DEFINE DEBUG_BAUD 9600
DEFINE DEBUG_MODE 0

DEFINE ADC_BITS 10 ' 10-bit Analog to digital
DEFINE ADC_SAMPLEUS 5 ' Set sampling time in uS

ANSELA = % 00000101 ' Pins A0 A2 = ADC
TRISA = % 11101111 ' Pin A4 = LED
TRISD = % 11111011 ' DEBUG
LATC.0 = 1 ' DEBUG
clear
LED VAR LATA.4
i var byte
j var word
bucket var WORD
ADCinput var WORD
mean var WORD
buckets var word[21]
outlier var WORD
LED = 1 'Proof of Life
PAUSE 2000
DEBUG 13,10,"READY",13,10
FVRCON = % 10000011
;ADCON0 = % 10000100 ;NOT USED
ADREF = % 00000000
ADCLK = 15
LED=0


Mainloop:
;NOTE an inputs sampled twice to overcome pbp poor adc ch changes
ADCIN 0, ADCinput
ADCIN 0, ADCinput
DEBUG 13,10,"R ",DEC ADCinput,9
ADCIN 2, ADCinput
ADCIN 2, ADCinput
DEBUG DEC ADCinput

PAUSE 500



GOTO Mainloop
end


i just tried it without the double adc reads on input change and it works ok , so that's not an issue anymore it seems
[i very rarely if ever use the adcin command , prefer to use asm sequences instead]