raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?
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Re: SOLVED: How can I reduce ADC drift
raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?
Warning I'm not a teacher
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Re: SOLVED: How can I reduce ADC drift
Coupling changed to AC.Originally Posted by richard
1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.
2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.
3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.
4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.
My Creality Ender 3 S1 Plus is a giant paperweight that can't even be used as a boat anchor, cause I'd be fined for polluting our waterways with electronic devices.
Not as dumb as yesterday, but stupider than tomorrow!
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Re: SOLVED: How can I reduce ADC drift
I shifted the results 2 bits, expecting to lose any jitter from 0 - 3, but I still get jitter.Code:ADCshift = NewADC0 >> 2
I bet it's when a number jumps an upper bit, like 00100011 to 01000100.
I'm using 10-bit ADC, so chopping 2 bits already bring me down to 256 increments.
Bringing it down more won't solve when it's a higher jump, like 00111111 to 01000000
EDIT: Divide by 4 doesn't help either, I still get jitter, even on the voltage-divider.
Last edited by Demon; - 24th February 2025 at 07:26.
My Creality Ender 3 S1 Plus is a giant paperweight that can't even be used as a boat anchor, cause I'd be fined for polluting our waterways with electronic devices.
Not as dumb as yesterday, but stupider than tomorrow!
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Re: SOLVED: How can I reduce ADC drift
changing my test to rs 2 digits
jitter negligible
Code:mean 159 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3596 0004,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 159 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 159 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3598 0002,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 159
Code:#CONFIG __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON __config _CONFIG5, _CP_OFF & _CPD_OFF #ENDCONFIG DEFINE OSC 32 DEFINE DEBUG_REG PORTD DEFINE DEBUG_BIT 2 ; if not used for pwr DEFINE DEBUG_BAUD 9600 DEFINE DEBUG_MODE 0 DEFINE ADC_BITS 10 ' 10-bit Analog to digital DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS ANSELA = % 00000001 ' Pin A0 = ADC TRISA = % 11101111 ' Pin A4 = LED TRISD = % 11111011 ' DEBUG LATD.2 = 1 ' DEBUG clear LED VAR LATA.4 i var byte j var word bucket var WORD ADCinput var WORD mean var WORD buckets var word[21] outlier var WORD LED = 1 'Proof of Life PAUSE 2000 DEBUG 13,10,"READY",13,10 FVRCON = % 10000011 ADCON0 = % 10010100 ADREF = % 00000000 ADPRE = 48 ADCLK = 32 ADCAP = 31 LED=0 Mainloop: mean = 0 for i = 0 to 9 ADCIN 0, ADCinput mean = mean + ADCinput next mean = mean/40 ;average divide 4 DEBUG "mean ",DEC mean,13,10 for j = 0 to 3599 ADCIN 0, ADCinput ADCinput=ADCinput>>2 bucket = mean-ADCinput i = bucket + 10 if i>20 then outlier = outlier + 1 else buckets[i]=buckets[i] + 1 endif 'DEBUG 13,10,"mean ",DEC mean," i ",dec i," read ",dec ADCinput,13,10 PAUSE 5 next DEBUG "readings " ,13,10 DEBUG dec4 buckets[0],",", dec4 buckets[1],"," , dec4 buckets[2],",", dec4 buckets[3],"," , dec4 buckets[4],"," DEBUG dec4 buckets[5],",", dec4 buckets[6],"," , dec4 buckets[7],",", dec4 buckets[8],"," , dec4 buckets[9]," " DEBUG dec4 buckets[10]," " DEBUG dec4 buckets[11],",", dec4 buckets[12],"," , dec4 buckets[13],",", dec4 buckets[14],"," , dec4 buckets[15],"," DEBUG dec4 buckets[16],",", dec4 buckets[17],"," , dec4 buckets[18],",", dec4 buckets[19],"," , dec4 buckets[20],13,10 DEBUG "outliers ",dec4 outlier DEBUG 13,10 for i = 0 to 20 buckets[i] = 0 next outlier = 0 GOTO Mainloop end
Warning I'm not a teacher
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Re: SOLVED: How can I reduce ADC drift
using the fvr gets slightly better result [mine is a 3.3v system]
Code:mean 255 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 255 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 255 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 255 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 255 readings 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 3600 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 outliers 0000 mean 255
Code:#CONFIG __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON __config _CONFIG5, _CP_OFF & _CPD_OFF #ENDCONFIG DEFINE OSC 32 DEFINE DEBUG_REG PORTD DEFINE DEBUG_BIT 2 ; if not used for pwr DEFINE DEBUG_BAUD 9600 DEFINE DEBUG_MODE 0 DEFINE ADC_BITS 10 ' 10-bit Analog to digital DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS ANSELA = % 00000001 ' Pin A0 = ADC TRISA = % 11101111 ' Pin A4 = LED TRISD = % 11111011 ' DEBUG LATD.2 = 1 ' DEBUG clear LED VAR LATA.4 i var byte j var word bucket var WORD ADCinput var WORD mean var WORD buckets var word[21] outlier var WORD LED = 1 'Proof of Life PAUSE 2000 DEBUG 13,10,"READY",13,10 FVRCON = % 10000010;2.048v ADCON0 = % 10000100 ADREF = % 00000011,fvr ADCLK = 16; faster clk LED=0 Mainloop: mean = 0 for i = 0 to 9 ADCIN 0, ADCinput mean = mean + ADCinput next mean = mean/40 DEBUG "mean ",DEC mean,13,10 for j = 0 to 3599 ADCIN 0, ADCinput ADCinput=ADCinput>>2 bucket = mean-ADCinput i = bucket + 10 if i>20 then outlier = outlier + 1 else buckets[i]=buckets[i] + 1 endif 'DEBUG 13,10,"mean ",DEC mean," i ",dec i," read ",dec ADCinput,13,10 PAUSE 5 next DEBUG "readings " ,13,10 DEBUG dec4 buckets[0],",", dec4 buckets[1],"," , dec4 buckets[2],",", dec4 buckets[3],"," , dec4 buckets[4],"," DEBUG dec4 buckets[5],",", dec4 buckets[6],"," , dec4 buckets[7],",", dec4 buckets[8],"," , dec4 buckets[9]," " DEBUG dec4 buckets[10]," " DEBUG dec4 buckets[11],",", dec4 buckets[12],"," , dec4 buckets[13],",", dec4 buckets[14],"," , dec4 buckets[15],"," DEBUG dec4 buckets[16],",", dec4 buckets[17],"," , dec4 buckets[18],",", dec4 buckets[19],"," , dec4 buckets[20],13,10 DEBUG "outliers ",dec4 outlier DEBUG 13,10 for i = 0 to 20 buckets[i] = 0 next outlier = 0 GOTO Mainloop end
Warning I'm not a teacher
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Re: SOLVED: How can I reduce ADC drift
My readings never jitter at 0000 or 1023, always rock solid.
It's when I start taking readings within the range that things go nuts.
My Creality Ender 3 S1 Plus is a giant paperweight that can't even be used as a boat anchor, cause I'd be fined for polluting our waterways with electronic devices.
Not as dumb as yesterday, but stupider than tomorrow!
|
Re: SOLVED: How can I reduce ADC drift
not reallyWe can't switch ADPCH manually between each Average?
it needs to take the number of readings to average in an uninterrupted exclusive sequence
once the average is obtained you can set a new channel and set the device to perform a new average
or cease averaging. a sequence cannot be interrupted for an additional extra adc read
or makes it worse if acquisition time is inadequate or marginal , the dummy read is most successfulI'm trying to switch ADPCH to 111100 = AVSS (Analog Ground) before each ADCIN to see if that fixes the problem.
not sure about this chip but when does channel change occur, a delay is probably required
i don't see any form of averaging here
Code:ADPCH = AVSS : adcin 0, ADCinput NewADC0 = 1023 - ADCinput ' inverted so pot goes from 0 to 1024 if NewADC0 <> oldadc0 then oldadc0 = NewADC0 ADCshift = NewADC0 / 4 LCDOUT $FE, $94+6, DEC4 oldadc0, " ", dec4 ADCshift : Pauseus 1 endif
Warning I'm not a teacher
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Re: SOLVED: How can I reduce ADC drift
to measure ac noise on rail , noise hopefully in mV and not to many of themCoupling changed to AC.
for any dc , logic measurementsCoupling changed to DC.
raw adc will never have no jitter1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.
the word you want here is resolution, if you had a 1k pot and 10 bit adc you could resolve it to 1 ohm steps in theory2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.
but adc is always has +- count , jitter free might get to 255 steps, you need to design for the outcome desired
depending on noise and needed resolution there are ways , from simple division, averaging or oversampling3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.
its not designed to average more than one ch and need exclusive use of the adc but have a go4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.
Warning I'm not a teacher
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Re: SOLVED: How can I reduce ADC drift
We can't switch ADPCH manually between each Average?23.0 ANALOG-TO-DIGITAL CONVERTER WITH COMPUTATION (ADC2) MODULE
The Analog-to-Digital Converter with Computation (ADC2) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit.
About that bug to ADCIN twice:
I'm trying to switch ADPCH to 111100 = AVSS (Analog Ground) before each ADCIN to see if that fixes the problem.23.1 ADC Configuration
Note: It is recommended that when switching from an ADC channel of a higher voltage to a channel of a lower voltage, the software selects the VSS channel before switching to the channel of the lower voltage.
They seem to mean when you change power rail, but maybe there's a bug when "the higher voltage" is within the same rail (like changing from 1V up to 4V).
I haven't studied your code yet, this is where I am at trying to get FVR and Average:
#CONFIG
__config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
__config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
__config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
__config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
__config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG
DEFINE OSC 32
DEFINE ADC_BITS 10 ' 10-bit Analog to digital
DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS
DEFINE LCD_DREG PORTB ' Set LCD data port
DEFINE LCD_DBIT 0 ' Set starting data bit
DEFINE LCD_RSREG PORTC ' Set LCD register select port
DEFINE LCD_RSBIT 4 ' Set LCD register select bit
DEFINE LCD_EREG PORTC ' Set LCD enable port
DEFINE LCD_EBIT 5 ' Set LCD enable bit
DEFINE LCD_BITS 4 ' Set LCD bus size
DEFINE LCD_LINES 4 ' Set number of lines on LCD
DEFINE LCD_COMMANDUS 1000 ' Set command delay time in microseconds
DEFINE LCD_DATAUS 50 ' Set data delay time in microseconds
FVRCON = %10000011 ' FIXED VOLTAGE REFERENCE CONTROL REGISTER
' bit 7 FVREN: Fixed Voltage Reference Enable bit
' ---> 1 = Fixed Voltage Reference is enabled
' 0 = Fixed Voltage Reference is disabled
' bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
' 1 = Fixed Voltage Reference output is ready for use
' 0 = Fixed Voltage Reference output is not ready or not enabled
' bit 5 TSEN: Temperature Indicator Enable bit(3)
' 1 = Temperature Indicator is enabled
' 0 = Temperature Indicator is disabled
' bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
' 1 = VOUT = VDD - 4VT (High Range)
' 0 = VOUT = VDD - 2VT (Low Range)
' bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
' 11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = Comparator FVR Buffer Gain is 1x, (1.024V)
' 00 = Comparator FVR Buffer is off
' bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
' ---> 11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = ADC FVR Buffer Gain is 1x, (1.024V)
' 00 = ADC FVR Buffer is off
'
' Note 1: FVRRDY is always ‘1’ for PIC16F18855/75 devices only.
' 2: Fixed Voltage Reference output cannot exceed VDD.
ADCON0 = %10000100 ' ADC CONTROL REGISTER 0
' bit 7 ADON: ADC Enable bit
' ---> 1 = ADC is enabled
' 0 = ADC is disabled
' bit 6 ADCONT: ADC Continuous Operation Enable bit
' 1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
' set) or until ADGO is cleared (regardless of the value of ADSOI)
' ---> 0 = ADGO is cleared upon completion of each conversion trigger
' bit 5 Unimplemented: Read as ‘0’
' bit 4 ADCS: ADC Clock Selection bit
' 1 = Clock supplied from FRC dedicated oscillator
' ---> 0 = Clock supplied by FOSC, divided according to ADCLK register
' bit 3 Unimplemented: Read as ‘0’
' bit 2 ADFRM0: ADC results Format/alignment Selection
' ---> 1 = ADRES and ADPREV data are right-justified
' 0 = ADRES and ADPREV data are left-justified, zero-filled
' bit 1 Unimplemented: Read as ‘0’
' bit 0 ADGO: ADC Conversion Status bit
' 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
' cleared by hardware as determined by the ADCONT bit
' ---> 0 = ADC conversion completed/not in progress
ADCON2 = %00101010 ' ADC CONTROL REGISTER 2
' bit 7 ADPSIS: ADC Previous Sample Input Select bits
' 1 = ADFLTR is transferred to ADPREV at start-of-conversion
' 0 = ADRES is transferred to ADPREV at start-of-conversion
' bit 6-4 ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits
' 111 = Reserved
' 110 = Reserved
' 101 through 000:
' If ADMD = 100:
' Low-pass filter time constant is 2ADCRS, filter gain is 1:1
' If ADMD = 001, 010 or 011:
' ---> The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(2)
' Otherwise:
' Bits are ignored
' bit 3 ADACLR: ADC Accumulator Clear Command bit
' 1 = Initial clear of ADACC, ADAOV, and the sample counter. Bit is cleared by hardware.
' 0 = Clearing action is complete (or not started)
' bit 2-0 ADMD<2:0>: ADC Operating Mode Selection bits(1)
' 111 = Reserved
' 101 = Reserved
' 100 = Low-pass Filter mode
' 011 = Burst Average mode
' ---> 010 = Average mode
' 001 = Accumulate mode
' 000 = Basic (Legacy) mode
' Note 1: See Table 23-3 for Full mode descriptions.
' 2: All results of divisions using the ADCRS bits are truncated, not rounded.
ADCNT = %00001000 ' ADC CONVERSION COUNTER REGISTER
' bit 7-0 ADRPT<7:0>: ADC Conversion Counter
' Counts the number of times that the ADC is triggered. Determines when the threshold is checked for
' the Low-Pass Filter, Burst Average, and Average Computation modes. Count saturates at 0xFF and
' does not roll-over to 0x00.
ADCLK = %00111111 ' ADC CLOCK SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADCCS<5:0>: ADC Conversion Clock Select bits
' ---> 111111 = FOSC/128
' 111110 = FOSC/126
' 111101 = FOSC/124
' •
' 000000 = FOSC/2
ADREF = %00000011 ' ADC REFERENCE SELECTION REGISTER
' bit 7-5 Unimplemented: Read as ‘0’
' bit 4 ADNREF: ADC Negative Voltage Reference Selection bit
' 1 = VREF- is connected to VREF- pin
' ---> 0 = VREF- is connected to AVSS
' bit 3-2 Unimplemented: Read as ‘0’
' bit 1-0 ADPREF: ADC Positive Voltage Reference Selection bits
' ---> 11 = VREF+ is connected to FVR_buffer 1
' 10 = VREF+ is connected to VREF+ pin
' 01 = Reserved
' 00 = VREF+ is connected to VDD
ADPCH = %00000000 ' ADC POSITIVE CHANNEL SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADPCH<5:0>: ADC Positive Input Channel Selection bits
' 111111 = Fixed Voltage Reference (FVR)
' 111110 = DAC1 output
' 111101 = Temperature Indicator
' ---> 111100 = AVSS (Analog Ground)
' 111011 = Reserved. No channel connected.
' •
' •
' •
' 100010 = ANE2 * 16F18877 only
' 100001 = ANE1 * 16F18877 only
' 100000 = ANE0 * 16F18877 only
' 011111 = AND7 * 16F18877 only
' 011110 = AND6 * 16F18877 only
' 011101 = AND5 * 16F18877 only
' 011100 = AND4 * 16F18877 only
' 011011 = AND3 * 16F18877 only
' 011010 = AND2 * 16F18877 only
' 011001 = AND1 * 16F18877 only
' 011000 = AND0 * 16F18877 only
' 010111 = ANC7
' 010110 = ANC6
' 010101 = ANC5
' 010100 = ANC4
' 010011 = ANC3
' 010010 = ANC2
' 010001 = ANC1
' 010000 = ANC0
' 001111 = ANB7
' 001110 = ANB6
' 001101 = ANB5
' 001100 = ANB4
' 001011 = ANB3
' 001010 = ANB2
' 001001 = ANB1
' 001000 = ANB0
' 000111 = ANA7
' 000110 = ANA6
' 000101 = ANA5
' 000100 = ANA4
' 000011 = ANA3
' 000010 = ANA2
' 000001 = ANA1
' 000000 = ANA0
ANSELA = %00001001 ' Pin A3 = ADC (voltage divider)
' Pin A0 = ADC (B5K)
ANSELB = %00000000
ANSELC = %00000000
TRISA = %00001001 ' Pin A3 = ADC input 3
' Pin A0 = ADC input 0
TRISB = %00000000
TRISC = %00000000
AVSS var byte
AVSS = %00111100 ' AVSS (Analog Ground)
ADCinput var WORD
OldADC0 var WORD
OldADC3 var WORD
NewADC0 var WORD
NewADC3 var WORD
ADCshift var WORD
Pause 100 ' Let PIC and LCD stabilize
ADCinput = 0
OldADC0 = 9999 : OldADC3 = 9999
NewADC0 = 0 : NewADC3 = 0
LCDOUT $FE, 1 : Pauseus 1
LCDOUT $FE, $80, " ADC test" : Pauseus 1
LCDOUT $FE, $94, "ADC0:" : Pauseus 1
LCDOUT $FE, $D4, "ADC3:" : Pauseus 1
Mainloop:
rem ADC 0
ADPCH = AVSS : adcin 0, ADCinput
NewADC0 = 1023 - ADCinput ' inverted so pot goes from 0 to 1024
if NewADC0 <> oldadc0 then
oldadc0 = NewADC0
ADCshift = NewADC0 / 4
LCDOUT $FE, $94+6, DEC4 oldadc0, " ", dec4 ADCshift : Pauseus 1
endif
rem ADC 3
ADPCH = AVSS : adcin 3, ADCinput
NewADC3 = ADCinput
if NewADC3 <> oldadc3 then
oldadc3 = NewADC3
ADCshift = NewADC3 / 4
LCDOUT $FE, $D4+6, DEC4 oldadc3, " ", dec4 ADCshift : Pauseus 1
endif
GOTO Mainloop
end
It still jitters. I'm sure I'm missing some parameters.
My Creality Ender 3 S1 Plus is a giant paperweight that can't even be used as a boat anchor, cause I'd be fined for polluting our waterways with electronic devices.
Not as dumb as yesterday, but stupider than tomorrow!
|
Re: SOLVED: How can I reduce ADC drift
Can't edit my post:
(like changing from 4V down to 1V)
And of course my code alignment is totally whacked...
My Creality Ender 3 S1 Plus is a giant paperweight that can't even be used as a boat anchor, cause I'd be fined for polluting our waterways with electronic devices.
Not as dumb as yesterday, but stupider than tomorrow!
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