Thanks for great help

I understand the NOP , but the LATB.0 = 1 ?

Where can I find information about LAT command/function and NOP

I assume this LAT = register
B = Port
.0 = Pin#
1/0 = High or Low

I'll test this code below and post the oscilloscope results
If someone can verify my code it it's correct for a 64Mhz clock speed.
used meConfig to generate the config section.
Thanks again


Code:
'  PIC18F25K22
'  Name    : Pulse Test
'  Date    : Oct 25-2024                                             
'**********************************************************************
;----[18F25K22 Hardware Configuration]------------------------------------------
#CONFIG
  CONFIG  FOSC = HSHP        ; HS oscillator (high power > 16 MHz)
  CONFIG  PLLCFG = ON        ; Oscillator multiplied by 4
  CONFIG  PRICLKEN = OFF     ; Primary clock can be disabled by software
  CONFIG  FCMEN = OFF        ; Fail-Safe Clock Monitor disabled
  CONFIG  IESO = OFF         ; Oscillator Switchover mode disabled
  CONFIG  PWRTEN = OFF       ; Power up timer disabled
  CONFIG  BOREN = SBORDIS    ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
  CONFIG  BORV = 190         ; VBOR set to 1.90 V nominal
  CONFIG  WDTEN = ON         ; WDT is always enabled. SWDTEN bit has no effect
  CONFIG  WDTPS = 32768      ; 1:32768
  CONFIG  CCP2MX = PORTC1    ; CCP2 input/output is multiplexed with RC1
  CONFIG  PBADEN = OFF       ; PORTB<5:0> pins are configured as digital I/O on Reset
  CONFIG  CCP3MX = PORTB5    ; P3A/CCP3 input/output is multiplexed with RB5
  CONFIG  HFOFST = ON        ; HFINTOSC output and ready status are not delayed by the oscillator stable status
  CONFIG  T3CMX = PORTC0     ; T3CKI is on RC0
  CONFIG  P2BMX = PORTB5     ; P2B is on RB5
  CONFIG  MCLRE = INTMCLR    ; RE3 input pin enabled; MCLR disabled
  CONFIG  STVREN = ON        ; Stack full/underflow will cause Reset
  CONFIG  LVP = OFF          ; Single-Supply ICSP disabled
  CONFIG  XINST = OFF        ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
  CONFIG  DEBUG = OFF        ; Disabled
  CONFIG  CP0 = OFF          ; Block 0 (000800-001FFFh) not code-protected
  CONFIG  CP1 = OFF          ; Block 1 (002000-003FFFh) not code-protected
  CONFIG  CP2 = OFF          ; Block 2 (004000-005FFFh) not code-protected
  CONFIG  CP3 = OFF          ; Block 3 (006000-007FFFh) not code-protected
  CONFIG  CPB = OFF          ; Boot block (000000-0007FFh) not code-protected
  CONFIG  CPD = OFF          ; Data EEPROM not code-protected
  CONFIG  WRT0 = OFF         ; Block 0 (000800-001FFFh) not write-protected
  CONFIG  WRT1 = OFF         ; Block 1 (002000-003FFFh) not write-protected
  CONFIG  WRT2 = OFF         ; Block 2 (004000-005FFFh) not write-protected
  CONFIG  WRT3 = OFF         ; Block 3 (006000-007FFFh) not write-protected
  CONFIG  WRTC = OFF         ; Configuration registers (300000-3000FFh) not write-protected
  CONFIG  WRTB = OFF         ; Boot Block (000000-0007FFh) not write-protected
  CONFIG  WRTD = OFF         ; Data EEPROM not write-protected
  CONFIG  EBTR0 = OFF        ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
  CONFIG  EBTR1 = OFF        ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
  CONFIG  EBTR2 = OFF        ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
  CONFIG  EBTR3 = OFF        ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
  CONFIG  EBTRB = OFF        ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG




DEFINE OSC 64
ANSELA = 0     
TRISA = %000000  
OSCTUNE = $40  
OSCCON = $70   
        




do


LATA.0 = 1
@ NOP
@ NOP
LATA.1 = 0
@ NOP
LATA.1 = 1
@ NOP
@ NOP
LATA.0 = 0


PAUSE 1000
LOOP
END