Originally Posted by
richard
post the code . no point guessing
Mainloop is in post #22.
Complete code PIC #1:
Code:
#CONFIG
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG
DEFINE OSC 32
SPLLEN CON %1 ' PLL enable
IRCF CON %1110 ' to enable 8 MHz
SCS CON %00 ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS
TXSTA = %00100100 ' DEFINE HSER_TXSTA 24h ' Enable transmit, BRGH = 1
' bit 7 CSRC: Clock Source Select bit
' Asynchronous mode:
' Don’t care
' Synchronous mode:
' 1 = Master mode (clock generated internally from BRG)
' 0 = Slave mode (clock from external source)
' bit 6 TX9: 9-bit Transmit Enable bit
' 1 = Selects 9-bit transmission
' 0 = Selects 8-bit transmission
' bit 5 TXEN: Transmit Enable bit(1)
' 1 = Transmit enabled
' 0 = Transmit disabled
' bit 4 SYNC: EUSART Mode Select bit
' 1 = Synchronous mode
' 0 = Asynchronous mode
' bit 3 SENDB: Send Break Character bit
' Asynchronous mode:
' 1 = Send Sync Break on next transmission (cleared by hardware upon completion)
' 0 = Sync Break transmission completed
' Synchronous mode:
' Don’t care
' bit 2 BRGH: High Baud Rate Select bit
' Asynchronous mode:
' 1 = High speed
' 0 = Low speed
' Synchronous mode:
' Unused in this mode
' bit 1 TRMT: Transmit Shift Register Status bit
' 1 = TSR empty
' 0 = TSR full
' bit 0 TX9D: Ninth bit of Transmit Data
' Can be address/data bit or a parity bit.
RCSTA = %10010000 'DEFINE HSER_RCSTA 90h ' Enable serial port & continuous receive
' bit 7 SPEN: Serial Port Enable bit
' 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
' 0 = Serial port disabled (held in Reset)
' bit 6 RX9: 9-bit Receive Enable bit
' 1 = Selects 9-bit reception
' 0 = Selects 8-bit reception
' bit 5 SREN: Single Receive Enable bit
' Asynchronous mode:
' Don’t care
' Synchronous mode – Master:
' 1 = Enables single receive
' 0 = Disables single receive
' This bit is cleared after reception is complete.
' Synchronous mode – Slave
' Don’t care
' bit 4 CREN: Continuous Receive Enable bit
' Asynchronous mode:
' 1 = Enables receiver
' 0 = Disables receiver
' Synchronous mode:
' 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
' 0 = Disables continuous receive
' bit 3 ADDEN: Address Detect Enable bit
' Asynchronous mode 9-bit (RX9 = 1):
' 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
' 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
' Asynchronous mode 8-bit (RX9 = 0):
' Don’t care
' bit 2 FERR: Framing Error bit
' 1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
' 0 = No framing error
' bit 1 OERR: Overrun Error bit
' 1 = Overrun error (can be cleared by clearing bit CREN)
' 0 = No overrun error
' bit 0 RX9D: Ninth bit of Received Data
' This can be address/data bit or a parity bit and must be calculated by user firmware.
Define HSER_BAUD 115200
DEFINE HSER_CLROERR 1 ' Clear overflow automatically
DEFINE HSER_SPBRGH 0
DEFINE HSER_SPBRG 68
BAUDCON.3 = 1 ' Enable 16 bit baudrate generator
ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000 ' ...not available
ANSELD = %00000000
ANSELE = %00000000
TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000
BlinkLED VAR LatB.5
RecvData var BYTE[11]
Pause 200 ' Let PIC and LCD stabilize
BlinkLED = 0
Start:
TXSTA.5 = 1 ' TXEN: Transmit Enable bit
hserout [ "[1]" ]
while TXSTA.1 = 0 ' Check TRMT: Transmit Shift Register Status bit
wend
TXSTA.5 = 0 ' <----- Causes Framing error after last byte !
hserin [ wait("["), STR RecvData\11\"]" ]
TXSTA.5 = 1 ' TXEN: Transmit Enable bit
hserout [ "[2]" ]
while TXSTA.1 = 0 ' Check TRMT: Transmit Shift Register Status bit
wend
TXSTA.5 = 0 ' <----- Causes Framing error after last byte !
Mainloop:
BlinkLED = 1
BlinkLED = 0
GOTO Mainloop
end
Complete code PIC #2:
Code:
#CONFIG
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG
include "DT_INTS-14.bas"
include "ReEnterPBP.bas"
ASM
INT_LIST macro ; IntSource, Label, Type, ResetFlag?
INT_Handler RX_INT, _ReceiveInterrupt, PBP, yes
endm
INT_CREATE ; Creates the interrupt processor
ENDASM
DEFINE OSC 32
SPLLEN CON %1 ' PLL enable
IRCF CON %1110 ' to enable 8 MHz
SCS CON %00 ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS
TXSTA = %00100100 ' DEFINE HSER_TXSTA 24h ' Enable transmit, BRGH = 1
' bit 7 CSRC: Clock Source Select bit
' Asynchronous mode:
' Don’t care
' Synchronous mode:
' 1 = Master mode (clock generated internally from BRG)
' 0 = Slave mode (clock from external source)
' bit 6 TX9: 9-bit Transmit Enable bit
' 1 = Selects 9-bit transmission
' 0 = Selects 8-bit transmission
' bit 5 TXEN: Transmit Enable bit(1)
' 1 = Transmit enabled
' 0 = Transmit disabled
' bit 4 SYNC: EUSART Mode Select bit
' 1 = Synchronous mode
' 0 = Asynchronous mode
' bit 3 SENDB: Send Break Character bit
' Asynchronous mode:
' 1 = Send Sync Break on next transmission (cleared by hardware upon completion)
' 0 = Sync Break transmission completed
' Synchronous mode:
' Don’t care
' bit 2 BRGH: High Baud Rate Select bit
' Asynchronous mode:
' 1 = High speed
' 0 = Low speed
' Synchronous mode:
' Unused in this mode
' bit 1 TRMT: Transmit Shift Register Status bit
' 1 = TSR empty
' 0 = TSR full
' bit 0 TX9D: Ninth bit of Transmit Data
' Can be address/data bit or a parity bit.
RCSTA = %10010000 'DEFINE HSER_RCSTA 90h ' Enable serial port & continuous receive
' bit 7 SPEN: Serial Port Enable bit
' 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
' 0 = Serial port disabled (held in Reset)
' bit 6 RX9: 9-bit Receive Enable bit
' 1 = Selects 9-bit reception
' 0 = Selects 8-bit reception
' bit 5 SREN: Single Receive Enable bit
' Asynchronous mode:
' Don’t care
' Synchronous mode – Master:
' 1 = Enables single receive
' 0 = Disables single receive
' This bit is cleared after reception is complete.
' Synchronous mode – Slave
' Don’t care
' bit 4 CREN: Continuous Receive Enable bit
' Asynchronous mode:
' 1 = Enables receiver
' 0 = Disables receiver
' Synchronous mode:
' 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
' 0 = Disables continuous receive
' bit 3 ADDEN: Address Detect Enable bit
' Asynchronous mode 9-bit (RX9 = 1):
' 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
' 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
' Asynchronous mode 8-bit (RX9 = 0):
' Don’t care
' bit 2 FERR: Framing Error bit
' 1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
' 0 = No framing error
' bit 1 OERR: Overrun Error bit
' 1 = Overrun error (can be cleared by clearing bit CREN)
' 0 = No overrun error
' bit 0 RX9D: Ninth bit of Received Data
' This can be address/data bit or a parity bit and must be calculated by user firmware.
Define HSER_BAUD 115200
DEFINE HSER_CLROERR 1 ' Clear overflow automatically
DEFINE HSER_SPBRGH 0
DEFINE HSER_SPBRG 68
BAUDCON.3 = 1 ' Enable 16 bit baudrate generator
ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000 ' ...not available
ANSELD = %00000000
ANSELE = %00000000 ' Pin E0 = ADC input
TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000
LEDblink var LatD.0
RecvData var BYTE[11]
UsartFlag Var byte
Pause 200 ' Let PIC and LCD stabilize
LEDblink = 0
UsartFlag = 0
@ INT_ENABLE RX_INT
goto Start
ReceiveInterrupt:
hserin [ wait("["), STR RecvData\11\"]" ]
UsartFlag = 1
@ INT_RETURN
Start:
Mainloop:
LEDblink = 1
if UsartFlag = 1 then
TXSTA.5 = 1
hserout [ "[0]" ]
while TXSTA.1 = 0 ' Check TRMT bit
wend
UsartFlag = 0
TXSTA.5 = 0
endif
LEDblink = 0
GOTO Mainloop
end
I prefer to use:
TXSTA = %00100100
RCSTA = %10010000
instead of:
DEFINE HSER_TXSTA 24h
DEFINE HSER_RCSTA 90h
So that I can actually see what bits are set (or is there more going on in the background with DEFINE?)
Re: Framing error if I disable transmitter after shift register is empty?
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