Framing error if I disable transmitter after shift register is empty?

[Ioannis]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

[Demon]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

I suppose so. This is from the datasheet for TXSTA register:

bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full

[Demon]

It's getting even dumber by the minute.

TX code on 1st 16F1937:

#CONFIG
 __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF 
 __CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG

DEFINE OSC 32
SPLLEN          CON %1              ' PLL enable
IRCF            CON %1110           ' to enable 8 MHz
SCS             CON %00             ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS

DEFINE  HSER_RCSTA 90h                          ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h                          ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1                          ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68
BAUDCON.3 = 1                                   ' Enable 16 bit baudrate generator

ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000                      ' ...not available
ANSELD = %00000000
ANSELE = %00000000
TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000

BlinkLED                    VAR LatB.5

    Pause 200

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout [   "[", 1, "]"]                             
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

Mainloop:
    BlinkLED = 1
    BlinkLED = 0
    goto mainloop
end

RX code on 2nd 16F1937:

#CONFIG
 __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF 
 __CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG

include "DT_INTS-14.bas"
include "ReEnterPBP.bas"
ASM
INT_LIST  macro    ; IntSource,        Label,  Type, ResetFlag?
        INT_Handler    RX_INT,  _ReceiveInterrupt,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

DEFINE OSC 32
SPLLEN          CON %1              ' PLL enable
IRCF            CON %1110           ' to enable 8 MHz
SCS             CON %00             ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS

DEFINE  HSER_RCSTA 90h              ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h              ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1              ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68
BAUDCON.3 = 1                       ' Enable 16 bit baudrate generator

ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000                      ' ...not available
ANSELD = %00000000
ANSELE = %00000000                      ' Pin E0 = ADC input

TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000

LEDblink            var PORTD.0

RecvData                var BYTE[11]

    LEDblink = 0
    goto Start

ReceiveInterrupt:
    hserin [ wait("["), STR RecvData\11\"]" ]

    TXSTA.5 = 1
    hserout [   "[", 0, "]"   ]                            
    while TXSTA.1 = 0              ' Check TRMT bit
    wend
    TXSTA.5 = 0

@ INT_RETURN

Start:
    Pause 200                           ' Let PIC and LCD stabilize
    
@   INT_ENABLE   RX_INT

Mainloop:
    LEDblink = 1
    LEDblink = 0
    GOTO Mainloop
end

The RX PIC has the exact same HSEROUT code:
- enable transmitter
- transmit data
- wait until buffer is empty
- disable transmitter


DISABLE transmitter causes a FRAMING ERROR on 1st PIC, but not on Ack message on 2nd PIC.



This has to be a really stupid error cause there's practically no code left.


EDIT: Does it make a difference if I disable transmitter inside the Interrupt routine?

EDIT SOME MORE: I moved the DISABLE out of the ISR and into Mainloop, it didn't make a difference during RX on the 2nd PIC.

[tumbleweed]

I'm not sure exactly what you intend to do, but TRMT gets asserted half-way into the STOP bit, so if you immediately disable the TX then the STOP bit will be half the time and generate a framing error.

The datasheet doesn't really specify that TXEN controls the state of the TX output pin (see datasheet section 25.1.1.1), but if it does return control back to the IO PORTC/TRISC registers then you'd have to make sure that the TX pin (RC6) is set to output high.

If you want it to be an input/tristate with an external pullup then set TRISC6.

[amgen]

checking your stuff........ if you use interrupts (DT ints), for RX interrupts, you would not use PB hserin in the int routine. Rather get the characters in your routine and store them in the locations you designated and advance counter and check for some beginning or ending character....... with this I receive up to 1000 characters and store them in ram on 18f with 4k ram..... you would fix for your code. If successful receive, raised a flag telling basic to process the data for whatever your looking for

'''-------------RCV INT ROUTINE----------------''''
RCint:
RCX=RCREG
'@ bcf RCSTA,4 
'@ bsf RCSTA,4   
'''@ CLRF CREN     ;RESET RCV overrun
'''@ SETF CREN

  

IF RCX=8 THEN     '''CHECK FOR BACK SPACE BS 8dec
SELECT CASE RCVindx
    CASE 0
        GOTO LEAVEOK1
    CASE 1
       RCVindx=RCVindx-1 :RCVOK=0
        RCVdata[RCVindx]=0    
       GOTO LEAVEOK1
    CASE IS >1
       RCVindx=RCVindx-1
       RCVdata[RCVindx]=0
       GOTO LEAVEOK1
END SELECT
ENDIF

if RCX = "[" then 
RCVindx=0:RCVok=1:DATAready=0   
goto leaveok 
endif  
if RCVok=0 then   LEAVEOK1    
if RCX = "]" then
rcvok=0:dataready=1 
endif 
    
leaveok:           'LEAVE AND STORE RCVD CHAR
RCVdata[RCVindx]=RCX
RCVindx=RCVindx+1
RCVdata[RCVindx]=0  'TACK A 0 AT END OF ARRAY
IF RCVindx > 999 THEN  
RCVindx=999
ENDIF
       
LEAVEOK1:          'LEAVE WITHOUT STORING RCVD CHAR
RCFLAG=1

[Demon]

checking your stuff........ if you use interrupts (DT ints), for RX interrupts, you would not use PB hserin in the int routine. Rather get the characters in your routine and store them in the locations you designated and advance counter and check for some beginning or ending character...

But the 2nd RX PIC receives perfectly. It's the 1st TX PIC that gives a framing error. And yet the 2nd RX gives an ACK using the HSEROUT structure, and it can DISABLE transmitter just fine.

I just don't get why PIC #1 cannot TXSTA.5 = 0, but PIC #2 can.

(I am going to keep that code on file, cause I'm sure it's going to be useful one day)


EDIT: I'm starting to think maybe I'm too dense to see the forest...

[Demon]

Question: why do people use TX INT?

I can understand why you want to use RX INT, cause you don't know when the data will be incoming, but I do know when the data is being transmitted.

I'm just wondering out loud that maybe I'm not using the best technique to transmit...?

[amgen]

don't give up on yourself or sell yourself short !...... it is a good project

[Demon]

I'm not sure exactly what you intend to do, ...

I'll be adding several more PICs on the network later, along with a tri-state BUSY line. The BUSY line will determine which PIC will be permitted to TRANSMIT at any given time. And that's why I ENABLE / TX / DISABLE, that code is in anticipation of more PICs being added.

...If you want it to be an input/tristate with an external pullup then set TRISC6

I have 4K7 pull-ups on both TX and RX pins. I only have RX set as Input. I plan on using a separate Busy line as tri-state.


I still don't see why PIC #1 gets a framing error, when PIC #2 doesn't and it's using essentially the exact same code...?