Framing error if I disable transmitter after shift register is empty?

[richard]

as best i can see the data sheet indicates that what u are trying should be ok


could hserout pacing be too slow to buffer tx data, and not really triggering back-back transmissions ?
if so then the last byte is still not sent yet.

if you used a decent chip you could make the tx pin open drain and not need this sort of worry

[Demon]

I'm using a 16F1937, and I've done this successully in the past on this PIC model.

Check this out, it's always after the last HSEROUT:

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout ["1"]
    hserout ["2"]
    hserout ["3"]
    hserout ["4"]
    hserout ["5"]                             
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
'    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

[Demon]

...could hserout pacing be too slow to buffer tx data, and not really triggering back-back transmissions ?
if so then the last byte is still not sent yet....

I thought this would ensure all bytes were transmitted?

    while TXSTA.1 = 0
    wend

...if you used a decent chip you could make the tx pin open drain and not need this sort of worry

I don't see why a 16F1937 could not do this reliably...?

[Demon]

The last byte DOES get transmitted.

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout ["1"]
    pause 1
    hserout ["2"]
    pause 1
    hserout ["3"]
    pause 1
    hserout ["4"]
    pause 1
    hserout ["5"]                             
    pause 1
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

Something happens when the transmitter is disabled:




I compare with my code and wiring on my old test circuit, and I can't see anything different...?

[Ioannis]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

[Demon]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

I suppose so. This is from the datasheet for TXSTA register:

bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full

[Demon]

It's getting even dumber by the minute.

TX code on 1st 16F1937:

#CONFIG
 __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF 
 __CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG

DEFINE OSC 32
SPLLEN          CON %1              ' PLL enable
IRCF            CON %1110           ' to enable 8 MHz
SCS             CON %00             ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS

DEFINE  HSER_RCSTA 90h                          ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h                          ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1                          ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68
BAUDCON.3 = 1                                   ' Enable 16 bit baudrate generator

ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000                      ' ...not available
ANSELD = %00000000
ANSELE = %00000000
TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000

BlinkLED                    VAR LatB.5

    Pause 200

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout [   "[", 1, "]"]                             
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

Mainloop:
    BlinkLED = 1
    BlinkLED = 0
    goto mainloop
end

RX code on 2nd 16F1937:

#CONFIG
 __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF 
 __CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG

include "DT_INTS-14.bas"
include "ReEnterPBP.bas"
ASM
INT_LIST  macro    ; IntSource,        Label,  Type, ResetFlag?
        INT_Handler    RX_INT,  _ReceiveInterrupt,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

DEFINE OSC 32
SPLLEN          CON %1              ' PLL enable
IRCF            CON %1110           ' to enable 8 MHz
SCS             CON %00             ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS

DEFINE  HSER_RCSTA 90h              ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h              ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1              ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68
BAUDCON.3 = 1                       ' Enable 16 bit baudrate generator

ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000                      ' ...not available
ANSELD = %00000000
ANSELE = %00000000                      ' Pin E0 = ADC input

TRISA = %00000000
TRISB = %00000000
TRISC = %10000000
TRISD = %00000000
TRISE = %00000000

LEDblink            var PORTD.0

RecvData                var BYTE[11]

    LEDblink = 0
    goto Start

ReceiveInterrupt:
    hserin [ wait("["), STR RecvData\11\"]" ]

    TXSTA.5 = 1
    hserout [   "[", 0, "]"   ]                            
    while TXSTA.1 = 0              ' Check TRMT bit
    wend
    TXSTA.5 = 0

@ INT_RETURN

Start:
    Pause 200                           ' Let PIC and LCD stabilize
    
@   INT_ENABLE   RX_INT

Mainloop:
    LEDblink = 1
    LEDblink = 0
    GOTO Mainloop
end

The RX PIC has the exact same HSEROUT code:
- enable transmitter
- transmit data
- wait until buffer is empty
- disable transmitter


DISABLE transmitter causes a FRAMING ERROR on 1st PIC, but not on Ack message on 2nd PIC.



This has to be a really stupid error cause there's practically no code left.


EDIT: Does it make a difference if I disable transmitter inside the Interrupt routine?

EDIT SOME MORE: I moved the DISABLE out of the ISR and into Mainloop, it didn't make a difference during RX on the 2nd PIC.

[tumbleweed]

I'm not sure exactly what you intend to do, but TRMT gets asserted half-way into the STOP bit, so if you immediately disable the TX then the STOP bit will be half the time and generate a framing error.

The datasheet doesn't really specify that TXEN controls the state of the TX output pin (see datasheet section 25.1.1.1), but if it does return control back to the IO PORTC/TRISC registers then you'd have to make sure that the TX pin (RC6) is set to output high.

If you want it to be an input/tristate with an external pullup then set TRISC6.