Framing error if I disable transmitter after shift register is empty?

[Demon]

TX pin can be set manually, BUT THIS IS ONLY MASKING THE PROBLEM, NOT A REAL SOLUTION.

See Richard's post #33 and onwards for details.

UsartTX             var LatC.6

    UsartTX = 1
    TXSTA.5 = 0

------------------------------------------------------

16F1937

Gutted my program to try to figure this out.

#CONFIG
 __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF 
 __CONFIG _CONFIG2, _WRT_OFF & _VCAPEN_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_LO & _LVP_OFF
#ENDCONFIG

DEFINE OSC 32
SPLLEN          CON %1              ' PLL enable
IRCF            CON %1110           ' to enable 8 MHz
SCS             CON %00             ' system clock determined by FOSC
OSCCON = (SPLLEN << 7) | (IRCF << 3) | SCS

DEFINE  HSER_RCSTA 90h                          ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h                          ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1                          ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68
BAUDCON.3 = 1                                   ' Enable 16 bit baudrate generator

ANSELA = %00000000
ANSELB = %00000000
'ANSELC = %00000000                      ' ...not available
ANSELD = %00000000
ANSELE = %00000000
TRISA = %00000000
TRISB = %00000000
TRISC = %00000000
TRISD = %00000000
TRISE = %00000000
BlinkLED                    VAR LatB.5

    Pause 500
    hserout ["Hello world", 10]

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
                
    hserout ["TEST", 10]                             

    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend

    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

Mainloop:
    BlinkLED = 1
    BlinkLED = 0
    goto mainloop
end

Checking on Logic Probe, the line remains LOW after the last HSEROUT (4K7 pull-up on pin).

Yet processing is normal if I comment TXSTA.5 = 0.

[richard]

as best i can see the data sheet indicates that what u are trying should be ok


could hserout pacing be too slow to buffer tx data, and not really triggering back-back transmissions ?
if so then the last byte is still not sent yet.

if you used a decent chip you could make the tx pin open drain and not need this sort of worry

[Demon]

I'm using a 16F1937, and I've done this successully in the past on this PIC model.

Check this out, it's always after the last HSEROUT:

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout ["1"]
    hserout ["2"]
    hserout ["3"]
    hserout ["4"]
    hserout ["5"]                             
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
'    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

[Demon]

...could hserout pacing be too slow to buffer tx data, and not really triggering back-back transmissions ?
if so then the last byte is still not sent yet....

I thought this would ensure all bytes were transmitted?

    while TXSTA.1 = 0
    wend

...if you used a decent chip you could make the tx pin open drain and not need this sort of worry

I don't see why a 16F1937 could not do this reliably...?

[Demon]

The last byte DOES get transmitted.

    TXSTA.5 = 1                     ' TXEN: Transmit Enable bit
    hserout ["1"]
    pause 1
    hserout ["2"]
    pause 1
    hserout ["3"]
    pause 1
    hserout ["4"]
    pause 1
    hserout ["5"]                             
    pause 1
    while TXSTA.1 = 0               ' Check TRMT: Transmit Shift Register Status bit
    wend
    TXSTA.5 = 0                     ' <----- Causes Framing error after last byte !

Something happens when the transmitter is disabled:




I compare with my code and wiring on my old test circuit, and I can't see anything different...?

[Ioannis]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

[Demon]

The Shift register you mentioned is the 2 Bytes Buffer?

Ioannis

I suppose so. This is from the datasheet for TXSTA register:

bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full