SOLVED - IOC works on B0 but not B5


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    Default Re: IOC works on B0 but not B5

    you need to read and adhere to the PBP3_PPS_notes.txt file in your pbp3 directory


    THIS FILE HAS BEEN UPDATED FOR PBP 3.1.1


    Devices with full Peripheral Pin Select (PPS) may be manipulated with the
    DEFINEs listed below. Default values shown may be subject to change due to
    Microchip pre-defined values. If in doubt, use the DEFINES to override defaults.




    --------------------------------------------------------------------------------


    Default output pins if no DEFINE is used:


    Pins: 8 14/16 20 28/40/48 64
    CCP1 RA2 RC5 RC5 RC2 RC2
    CCP2 RA5 RC3 RC3 RC1 RC1
    CCP3 RA2 RA2 RB5 RC3
    CCP4 RC1 RA4 RB0 RG3


    RX1 RA1 RC5 RB5 RC7 RC7
    TX1 RA0 RC4 RB7 RC6 RC6
    RX2 RC1 RC1 RB5* RG2
    TX2 RC2 RC2 RB4* RG1


    * RX2/TX2 defaults changed for some devices in PBP 3.1.1 to avoid ICSP lockout.


    Note that on some devices, any pin that is assigned to a CCP channel
    may not function as normal I/O. If a pin's CCP default inhibits a
    desired function, you can cancel the default as described below.


    --------------------------------------------------------------------------------
    HPWM


    Use the following PBP DEFINE statements to specify the output pins for HPWM.
    Check the Microchip datasheet (Peripheral Pin Select PPS) for the pins allowed
    on each CCP channel. The PPS peripheral will automatically be configured
    for the specified output pin upon execution of HPWM. When used on devices
    without PPS, these defines will only control the Data Direction SFRs (TRIS).


    These defines set PPS SFRs only once at program initialization. You may
    change the PWM output pin at any point in your program code by modifying
    the PPS SFRs. The HPWM command may be used without these DEFINEs if you
    manually configure the PPS and TRIS SFRs.


    As noted below, you may use DEFINE CCPx_REG 0 to inhibit PPS inititalization
    and automatic TRIS settings for any channel. You should do this if you plan
    to relocate pins with PPS settings at run-time to avoid erroneous TRIS settings.




    DEFINE CCP1_REG PORTC 'Channel-1 port
    DEFINE CCP1_BIT 2 'Channel-1 bit
    DEFINE CCP2_REG PORTC 'Channel-2 port
    DEFINE CCP2_BIT 1 'Channel-2 bit
    DEFINE CCP3_REG PORTC 'Channel-3 port
    DEFINE CCP3_BIT 3 'Channel-3 bit
    DEFINE CCP4_REG PORTG 'Channel-4 port
    DEFINE CCP4_BIT 3 'Channel-4 bit
    DEFINE CCP5_REG PORTG 'Channel-5 port
    DEFINE CCP5_BIT 4 'Channel-5 bit
    DEFINE CCP6_REG PORTE 'Channel-6 port
    DEFINE CCP6_BIT 6 'Channel-6 bit
    DEFINE CCP7_REG PORTE 'Channel-7 port
    DEFINE CCP7_BIT 7 'Channel-7 bit


    DEFAULT CCP PINS SET FOR UNUSED HPWM CHANNELS! If CCP_REG DEFINEs are set
    for unused channels, either explicitly or by default, the ports/pins specified
    as CCP/PWM outputs may not function as normal I/O until the PPS SRFs are cleared
    in your program code. To remove a default setting, define the CCPx_REG as 0,
    for example:


    DEFINE CCP1_REG PORTC 'Channel-1 port
    DEFINE CCP1_BIT 2 'Channel-1 bit
    DEFINE CCP2_REG 0 'Channel-2 UNUSED
    DEFINE CCP2_BIT 0 'Channel-2 bit
    DEFINE CCP3_REG 0 'Channel-3 UNUSED
    DEFINE CCP3_BIT 0 'Channel-3 bit
    DEFINE CCP4_REG 0 'Channel-4 UNUSED
    DEFINE CCP4_BIT 0 'Channel-4 bit


    Oooops, added edit to your post by mistake.... (- Demon)
    Last edited by Demon; - 13th September 2024 at 03:20.
    Warning I'm not a teacher

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