Thank you Henrik for you prompt reply.
The Receiver PIC's GPIO.5 is indeed configured as an input and the two systems do share a common ground.
Transmit PIC - GPIO.2 is set as an output and the outbound packet is sent by SEROUT DataOut,1,[ProgID,IDByte]
Receive PIC - GPIO.5 is set as an input and is configured to receive the packet by SERIN PrgIn,1,5000,PassProg,[ProgIDRx],IDByteRx
I didn't include the transmitter PIC code because the oscilloscope verified that the packet is being sent.
I wonder... what logic state should SERIN be idling at? I have it at logic high to generate a "mark" condition.
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