18F26K80 Serial setting sanity check and 4xPLL.

[tumbleweed]

How are you verifying the freq?

Could you post your whole setup, including the config?

[retepsnikrep]

The code is massive.

I have a 1hz led timer1 interrupt flasher routine.

It's only working at 1/4 speed with the 20mhz resonator but works correctly at 64mhz with the internal osc.

[retepsnikrep]

'-------------------------- General 18F26K80 configuration ---------------------

#CONFIG
    CONFIG  RETEN = OFF           ; Ultra low-power regulator is Enabled (Controlled by SRETEN bit)
    CONFIG  INTOSCSEL = HIGH      ; High power mode during Sleep
    CONFIG  SOSCSEL = DIG         ; Disabled RC0 & RC1 I/0
    CONFIG  XINST = OFF           ; Disabled
    CONFIG  FOSC = HS2            ; External 20mhz Resonator
    CONFIG  PLLCFG = ON           ; Enabled
    CONFIG  FCMEN = OFF           ; Disabled
    CONFIG  IESO = OFF            ; Disabled
    CONFIG  PWRTEN = OFF          ; Disabled
    CONFIG  BOREN = OFF           ; Disabled 
    CONFIG  BORV = 3              ; 1.8V
    CONFIG  BORPWR = ZPBORMV      ; ZPBORMV instead of BORMV is selected
    CONFIG  WDTEN = OFF           ; WDT disabled in hardware; SWDTEN bit disabled
    CONFIG  WDTPS = 512           ; WDTPS 1:256  = 1.024 Second Timeout
    CONFIG  CANMX = PORTB         ; ECAN TX and RX pins are located on RB2 and RB3, respectively
    CONFIG  MSSPMSK = MSK7        ; 7 Bit address masking mode
    CONFIG  MCLRE = OFF           ; MCLR Enabled, RE3 Disabled
    CONFIG  STVREN = ON           ; Enabled
    CONFIG  BBSIZ = BB2K          ; 2K word Boot Block size
    CONFIG  CP0 = OFF             ; Disabled
    CONFIG  CP1 = OFF             ; Disabled
    CONFIG  CP2 = OFF             ; Disabled
    CONFIG  CP3 = OFF             ; Disabled
    CONFIG  CPB = OFF             ; Disabled
    CONFIG  CPD = OFF             ; Disabled
    CONFIG  WRT0 = OFF            ; Disabled
    CONFIG  WRT1 = OFF            ; Disabled
    CONFIG  WRT2 = OFF            ; Disabled
    CONFIG  WRT3 = OFF            ; Disabled
    CONFIG  WRTC = OFF            ; Disabled
    CONFIG  WRTB = OFF            ; Disabled
    CONFIG  WRTD = OFF            ; Disabled
    CONFIG  EBTR0 = OFF           ; Disabled
    CONFIG  EBTR1 = OFF           ; Disabled
    CONFIG  EBTR2 = OFF           ; Disabled
    CONFIG  EBTR3 = OFF           ; Disabled
    CONFIG  EBTRB = OFF           ; Disabled
#ENDCONFIG  

'*******************************************************************************
'**************************  PBP Basic Defines  ********************************
'*******************************************************************************  

DEFINE OSC 40           '80mhz  (If overclocking at 96mhz set define to 48mhz ot if 80mhz set at 40mhz)
DEFINE NO_CLRWDT 1      'No Clear WDT Instructions added

'***********************   Direct Pic Register Settings ************************

OSCCON  = %00001000     'External Resonator  
OSCCON2 = %00000000     'Clear
HLVDCON = %00000000		'HLVCON Disabled   

T1CON = %00110000       'Timer 1 Setup. 
'TRISA = %11111111 		'SET PORTA.0-7 Inputs
TRISA = %00111111 		'SET PORTA.0-5 Inputs 6,7 Outputs
TRISB = %00001000		'SET PORTB.3 Input rest as Outputs 
TRISC = %10010000		'SET PORTC.4,7 Inputs rest as Outputs

ANCON0 = %00000001      'Analog Inputs on A0
ANCON1 = %00000000      'No Analog Inputs 

ADCON2 = %00011110	    'SETUP ADC FOSC/64 LEFT JUSTIFY TAD 6  
ADCON1 = %00000000	    'SETUP ADC SET REFV to VDD & VSS AN0 
ADCON0 = %00000011	    'SETUP ADC & ENABLE ADC MODULE & START CONVERSION    

SLRCON = %00000000      'Ports slew at standard rate!

SSPSTAT = %11000000     'Configure SPI Module      
SSPCON1 = %00101010     'Enable SPI Master Mode Fosc/8 (10mhz) Clock idle low
SSPCON2 = %00000000     'Configure SPI Module

'bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode bits(3)

'0010 = SPI Master mode: clock = FOSC/64  (1mhz)
'0001 = SPI Master mode: clock = FOSC/16  (4mhz)
'1010 = SPI Master mode: clock = FOSC/8   (8mhz at 64fosc) (10mhz at 80fosc) (12mhz at 96fosc)
'0000 = SPI Master mode: clock = FOSC/4   (16mhz)  (Doesn't Work!)      

'Eusart 1 (64mhz FOSC)  'Serial/Video Comms (16mhz x 4)
'DEFINE HSER_RCSTA 90h   'Enable serial port & continuous receive
'DEFINE HSER_TXSTA 24h   'Enable transmit, BRGH = 1
'DEFINE HSER_CLROERR 1   'Clear overflow automatically
'DEFINE HSER_SPBRG 22    '57600 Baud @ 64MHz, -0.44%   (277 Decimal = $115) 
'define HSER_SPBRGH 1
'BAUDCON1.3 = 1          'Enable 16 bit baudrate generator

''Eusart 1 (80mhz FOSC)  'Serial/Video Comms (20mhz x 4)
DEFINE HSER_RCSTA 90h   'Enable serial port & continuous receive
DEFINE HSER_TXSTA 24h   'Enable transmit, BRGH = 1
DEFINE HSER_CLROERR 1   'Clear overflow automatically
DEFINE HSER_SPBRG 90    '57600 Baud @ 80MHz, -0.064%   (346 Decimal = $15A) 
define HSER_SPBRGH 1
BAUDCON1.3 = 1          'Enable 16 bit baudrate generator   

''Eusart 1 (96mhz FOSC)  'Serial/Video Comms (24mhz x 4)
'DEFINE HSER_RCSTA 90h   'Enable serial port & continuous receive
'DEFINE HSER_TXSTA 24h   'Enable transmit, BRGH = 1
'DEFINE HSER_CLROERR 1   'Clear overflow automatically
'DEFINE HSER_SPBRG 160   '57600 Baud @ 96MHz, -0.080%   (416 Decimal = $1A0) 
'define HSER_SPBRGH 1
'BAUDCON1.3 = 1          'Enable 16 bit baudrate generator

[retepsnikrep]

I tried changing chip, no difference.

Still stuck at 1/4 speed and PLL not activating.

Hmm I wonder if my resonator marked 20mhz really is a 20mhz one!!

[tumbleweed]

I don't have any 20MHz xtals to try.

FWIW, I was able to get an 18F26K80 running at 80MHz with an external 20MHz osc into OSC1/CLKIN (using CONFIG = EC3).
The 4x PLL worked using either CONFIG PLLCFG = ON or CONFIG PLLCFG = OFF and setting OSCTUNE.PLLEN = 1.

I didn't even have a cap on the VDDCORE pin, and it worked with VDD down to 3V.

According to the datasheet EC and HS modes use the same clock tree, so I would think if you're using HS2 mode with a 20MHz xtal it would work too.

[retepsnikrep]

Hi all I'm still fiddling with this.

Any new ideas on why it might not run at 80mhz with external resonator?

[tumbleweed]

Did you try powering up with the PLL off and then turning it on later?

Try changing some of the CONFIG settings

    CONFIG FOSC = HS2		; HS oscillator (High power, 16 MHz - 25 MHz)
    CONFIG PLLCFG = OFF		; Disabled
    CONFIG PWRTEN = ON		; Enabled
    CONFIG BOREN = SBORDIS	; Enabled in hardware, SBOREN disabled
    CONFIG BORV = 0		; 3.0V

and then at startup

 
'***********************   Direct Pic Register Settings ************************
OSCCON  = %00000000     'SCS[1:0] = 00, Default primary oscillator
OSCCON2 = %00000000     'Clear

' enable the 4xPLL
delayms 100	' allow some time for osc and power to stabilize
OSCTUNE.6 = 1	' PLLEN = 1