OWOUT Glitch


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  1. #1
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    Default Re: OWOUT Glitch

    it doesn't, LOW lata.6 turns the PLL OFF as with HIGH lata.6

    porta address + 18 = trisa
    lata address + 18 = osctune on that chip [it varies]

    all pbp "high level" commands that set a pin direction use a fixed offset to get to the tris reg
    it simply will not work correctly from a LATx offset
    Warning I'm not a teacher

  2. #2


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    Default Re: OWOUT Glitch

    Thanks that explains it..

  3. #3
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    Default Re: OWOUT Glitch

    using pbp "high level" commands with LATX registers is a great way to introduce hard to find bugs in your code
    5 stars
    Warning I'm not a teacher

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