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Re: PIC18FxxQ43 Version of DT_INTS
On the Q43 (and most recent PIC18's with the VIC), the SFR registers have been moved down in memory starting at BANK 0,
so general purpose RAM no longer starts there. The access bank used to be part of that, but no more.
For the Q43, the access RAM is now at 0x500-0x55F, and the SFR access bank is 0x460-0x4FF.
Anything located outside those addresses require the bank select register (BSR) to be set appropriately.
Many asm instructions have a ", a" field at the end, where 'a' specifies the RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
The TMR1 registers are located in bank 3, so you can't use asm instructions that end in ", 0" to access them.
You'd have to set the BSR with a 'movlb' (or use mpasm 'BANKSEL reg') and change the ", 0" to ", 1" (or drop it off).
If you don't specify the ", a" part MPASM is usually pretty good at figuring out when it needs a = ", 0", or ", 1", but it's up to you to set the BSR if needed.
Datasheet sections 44 (Instruction Set Summary) and section 46 (Register Summary) have all the info you need, once you get your head wrapped around how it works.
So, looking at your timer macros LOAD_TIMER is probably ok since the 'MOVE?xx' macros set the BSR, but if the other two are used on their own they'll need to change (adding instructions which will change the timing).
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