I'm turning crazy ... I see the problem also without the PBP LONG option

I copy here the full code to show the problem.

Code:
DEFINE RESET_ORG 1EC00h
' device=PIC18F67K22
' PBP LONG option enabled

#CONFIG
    CONFIG  RETEN = ON          ; Enabled
    CONFIG  INTOSCSEL = LOW      ; LF-INTOSC in High-power mode during Sleep
    CONFIG  SOSCSEL = DIG        ; 
    CONFIG  XINST = OFF           ; Disabled
    CONFIG FOSC = INTIO2	    ; Internal RC oscillator
    CONFIG  PLLCFG = OFF           ; Enabled
    CONFIG  FCMEN = OFF           ; Disabled
    CONFIG  IESO = OFF            ; Disabled
    CONFIG  PWRTEN = OFF          ; Disabled
    CONFIG  BOREN = SBORDIS       ; Enabled in hardware, SBOREN disabled
    CONFIG  BORV = 2              ; 2.0V
    CONFIG  BORPWR = ZPBORMV      ; ZPBORMV instead of BORMV is selected
    CONFIG  WDTEN = OFF
    CONFIG  WDTPS = 256           ; 1:256
    CONFIG  RTCOSC = SOSCREF      ; RTCC uses SOSC
    CONFIG  CCP2MX = PORTC        ; RC1
    CONFIG  MSSPMSK = MSK7        ; 7 Bit address masking mode
    CONFIG  MCLRE = ON            ; MCLR Enabled, RG5 Disabled
    CONFIG  STVREN = ON           ; Enabled
    CONFIG  BBSIZ = BB2K          ; 2K word Boot Block size
    CONFIG  DEBUG = OFF           ; Disabled
    CONFIG  CP0 = OFF             ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
    CONFIG  CP1 = OFF             ; Block 1 (004000-007FFFh) code-protected
    CONFIG  CP2 = OFF             ; Block 2 (008000-00BFFFh) code-protected
    CONFIG  CP3 = OFF             ; Block 3 (00C000-00FFFFh) code-protected
    CONFIG  CP4 = OFF             ; Block 4 (010000-013FFFh) code-protected
    CONFIG  CP5 = OFF             ; Block 5 (014000-017FFFh) code-protected
    CONFIG  CP6 = OFF             ; Block 6 (01BFFF-018000h) code-protected
    CONFIG  CP7 = OFF             ; Block 7 (01C000-01FFFFh) code-protected
    CONFIG  CPB = ON             ; Boot Block (000000-0007FFh) code-protected
    CONFIG  CPD = OFF             ; Data EEPROM code-protected
    CONFIG  WRT0 = OFF            ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
    CONFIG  WRT1 = OFF            ; Block 1 (004000-007FFFh) not write-protected
    CONFIG  WRT2 = OFF            ; Block 2 (008000-00BFFFh) not write-protected
    CONFIG  WRT3 = OFF            ; Block 3 (00C000-00FFFFh) not write-protected
    CONFIG  WRT4 = OFF            ; Block 4 (010000-013FFFh) not write-protected
    CONFIG  WRT5 = OFF            ; Block 5 (014000-017FFFh) not write-protected
    CONFIG  WRT6 = OFF            ; Block 6 (01BFFF-018000h) not write-protected
    CONFIG  WRT7 = OFF            ; Block 7 (01C000-01FFFFh) not write-protected
    CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) not write-protected
    CONFIG  WRTB = OFF            ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
    CONFIG  WRTD = OFF            ; Data EEPROM not write-protected
    CONFIG  EBRT0 = OFF           ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT1 = OFF           ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT2 = OFF           ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT3 = OFF           ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT4 = OFF           ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT5 = OFF           ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT6 = OFF           ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT7 = OFF           ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRTB = OFF           ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
	#ENDCONFIG

	DEFINE		OSC			8
	DEFINE		HSER2_RCSTA	90H
	DEFINE  		HSER2_TXSTA  	24H
	DEFINE 		HSER2_BAUD	19200
	DEFINE		HSER2_CLROERR	1

	CLEAR
	OSCCON		=%01100000			; Primary oscillator, internal 8MHz
	OSCCON2.0	=1
	OSCTUNE.7	=1
	Adr			VAR	WORD

loop1:
    FOR Adr=1000 TO 1005
	HSEROUT2 ["test1: ",13,10]			' -->>>> this works always
        HSEROUT2 ["test2: ", DEC4 Adr,13,10] 	' -->>>> this works only if you comment the first line "DEFINE RESET_ORG 1EC00h"
    NEXT Adr
    PAUSE 1000
    CLEARWDT
    goto loop1