Code:
'****************************************************************'* Name : MAX30102 FOR PIC 18 test *
'* Author : Richard *
'* Notice : *
'* : *
'* Date : 9/1/2022 *
'* Version : 1.0 *
'* Notes : MAX30102 *
'* :18f26k22 @64Mhz *
'****************************************************************
#CONFIG ; The PBP configuration for the PIC18F26K22 is:
CONFIG FOSC = INTIO67
CONFIG PLLCFG = OFF ;Oscillator multiplied by 4
CONFIG PRICLKEN = ON ;Primary clock enabled
CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ;Oscillator Switchover mode disabled
CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect ;|
CONFIG WDTPS = 32768 ; 1:32768 ---> HERE enable the watchdog timer with a 1:32768 postscale;|
CONFIG PWRTEN = ON
CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Disabled
CONFIG CP0 = OFF ; Block 0 (000800-003FFFh) not code-protected
CONFIG CP1 = OFF ; Block 1 (004000-007FFFh) not code-protected
CONFIG CP2 = OFF ; Block 2 (008000-00BFFFh) not code-protected
CONFIG CP3 = OFF ; Block 3 (00C000-00FFFFh) not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD = OFF ; Data EEPROM not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-003FFFh) not write-protected
CONFIG WRT1 = OFF ; Block 1 (004000-007FFFh) not write-protected
CONFIG WRT2 = OFF ; Block 2 (008000-00BFFFh) not write-protected
CONFIG WRT3 = OFF ; Block 3 (00C000-00FFFFh) not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ; Data EEPROM not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
CONFIG EBTR3 = OFF ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG
'define I2C_SLOW 1
define OSC 64
OSCCON = %01110000 ; 16Mhz
OSCTUNE.6 = 1 ; Enable 4x PLL
while ! osccon2.7 :WEND ; to make sure the pll has stabilised before you run any other code
TRISC = %11011000
ANSELC=0
#DEFINE DEBUGING 1
#IFNDEF DEBUGING
DEFINE HSER_RCSTA 90h ' Enable serial port & continuous receive
DEFINE HSER_TXSTA 24h ' Enable transmit, BRGH = 1
DEFINE HSER_CLROERR 1 ' Clear overflow automatically
DEFINE HSER_SPBRG 160 ' 38400 Baud @ 64MHz, -0.08%
SPBRGH = 1
BAUDCON.3 = 1 ' Enable 16 bit baudrate generator
#ELSE
DEFINE DEBUG_REG PORTB
DEFINE DEBUG_BIT 7
DEFINE DEBUG_BAUD 9600
DEFINE DEBUG_MODE 0
ANSELB=0
LATB.7=1
#ENDIF
SDA var portc.4 ' DATA PIN
SCL VAR portc.3 ' CLOCK PIN
Timeout cON 2000
reg var BYTE
fifo var byte[6]
addr var byte
REVISION var byte
PARTID var byte
buffer var byte[1152]
ptr var byte
btr var byte
index var word
;----------------------- REGISTER -------------------------
REG_TEMP_INT con $1F
REG_TEMP_FRAC con $20
REG_TEMP_CONFIG con $21
REG_PART_REVISION con $FE
REG_MODE con $09
REG_SPO2_CONFIG con $0A ;SPO2_ADC_RGE[6:5]SPO2_SR[4:2]LED_PW[1:0]
REG_LED1_PA con $0C
REG_LED2_PA con $0D
FIFO_WR_PTR con $04 ;FIFO_WR_PTR[4:0]
FIFO_RD_PTR con $06
FIFO_DATA con $07
FIFO_CONFIG con $08 ;FIFO_A_FULL[3:0] SMP_AVE[7:5]
STATUS1 con 0 ;A_FULL[7]
' -----------------------------------------------------------------------------|
#IFDEF DEBUGING
PAUSE 2000
DEBUG 13,10, "READY"
#ENDIF
ADDR = $ae ; addr is 0x57 << 1
reg= REG_PART_REVISION
i2cread SDA,scl,ADDR,reg,[REVISION,PARTID]
reg= REG_MODE
i2cwrite SDA,scl,ADDR,reg,[3]
reg= REG_SPO2_CONFIG
i2cwrite SDA,scl,ADDR,reg,[$30]
reg = REG_LED2_PA
i2cwrite SDA,scl,ADDR,reg,[2]
reg = REG_LED1_PA
i2cwrite SDA,scl,ADDR,reg,[2]
reg = FIFO_CONFIG
i2cwrite SDA,scl,ADDR,reg,[16]
#IFNDEF DEBUGING
HSEROUT [$73,$03,$04,$11,$ff,$ff,"PART ID: 0X",hex PARTID,"/0X", hex REVISION,$00]
Hserin timeout,error,[wait(6)]
#ELSE
DEBUG 13,10, "PART ID: 0X",hex PARTID,"/0X",hex REVISION
#ENDIF
'********************************************************************************
start:
reg= REG_TEMP_CONFIG
i2cwrite SDA,scl,ADDR,reg,[1]
reg= REG_TEMP_INT
i2cread sda,scl,ADDR,reg,[fifo[0],fifo[1]]
#IFNDEF DEBUGING
HSEROUT [$73,$05,$0A,$11,$07,$E0,"TEMP: ",DEC fifo[0],".",DEC2( fifo[1]<<6),$00]
Hserin timeout,error,[wait(6)]
#ELSE
DEBUG 13,10, "TEMP: ",DEC fifo[0],".",DEC2( fifo[1]<<6)
#ENDIF
GOSUB AQUIRE
pause 5000
goto start
aquire:
reg= FIFO_WR_PTR
i2cwrite SDA,scl,ADDR,reg,[0]
reg= FIFO_RD_PTR
i2cwrite SDA,scl,ADDR,reg,[0]
FOR index = 0 TO 1151 STEP 0
btr =0
reg= STATUS1
WHILE btr&$80=0
i2cread sda,scl,ADDR,reg,[btr]
WEND
reg= FIFO_RD_PTR
i2cread SDA,scl,ADDR,reg,[btr]
btr = (btr- ptr) & 31
WHILE btr
reg = FIFO_DATA
i2cread sda,scl,ADDR,reg,[buffer[index],buffer[index+1],buffer[index+0],buffer[index+5],buffer[index+4],buffer[index+3]]
index=index+6
btr=btr-1
ptr = (Ptr+1) & 31
WEND
pause 200 ; no sure about this either
NEXT
FOR index = 0 TO 1151 STEP 0
DEBUG 13,10,HEX2 buffer[index+0],HEX2 buffer[index+1],9,HEX2 buffer[index+3],HEX2 buffer[index+4]
index=index+6
NEXT
RETURN
Re: Heart rate sensor MAX30102
Bookmarks