not sure what your expecting from the output , it works for men on out 2
i used this code / with fvr and vdd for vsource+ both work
the pickit3 i used did not seem to load the out2 pin so i left it connected for tests

i did make portc digital . i also tried setting out2 pin as an input ,it makes no difference either way making it analog is not relevent

Code:
;********************************************************************************'*  Name    : DACtest.pbp                               #### 1/2 Working code ####   *
'*  Date    : 02/08/20                                                           *
'*  Device  : 16F1705                                                            *
'*  Version : 1     (PBP 3.0.10.4)                                               *
'*********************************************************************************
'
'=========================================================================================================
'        CONFIGURE DEVICE
'=========================================================================================================
#CONFIG ; 16F1705
    __config _CONFIG1, _FOSC_INTOSC & _WDTE_ON & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _BOREN_ON & _CLKOUTEN_OFF
    __config _CONFIG2, _WRT_OFF & _PPS1WAY_OFF & _ZCDDIS_OFF & _PLLEN_OFF & _STVREN_ON & _BORV_LO & _LPBOR_OFF & _LVP_OFF	   
#ENDCONFIG


' Connections as follows:
'     ****16F1705 PIC**** Comments
'
' Vdd          (pin 1)    5 volts.      
'         RA5  (pin 2)    T1clk.                Spare.       
'         RA4  (pin 3)	  AN3, T1G.             Spare.
' MCLR    RA3  (pin 4)    IOC.  Pull High 10k.  Spare.
'         RC5  (pin 5)	  Opamp2in+, CCP1.      Spare.
'         RC4  (pin 6)    Opamp2in-.            Serin for setting from laptop (9600).
'         RC3  (pin 7)    AN7, Opamp2Out, CCP2. Serout for monitoring (9600).      
'         RC2  (pin 8)    AN6, Opamp1Out.       Spare.
'         RC1  (pin 9)    AN5, Opamp1in-.       Spare.
'         RC0  (pin 10)   AN4, Opamp1in+.       Spare.
'         RA2  (pin 11)   AN2, DAC1out2.        DAC alternate output.
' ICSPclk RA1  (pin 12)   AN1, Vref+.           Spare.
' ICSPdat RA0  (pin 13)   AN0, DAC1out1.        Default output voltage from DAC.
' Vss  Ground  (pin 14)   


'=========================================================================================================
'        PIN ASSIGNMENTS, SYSTEM CONSTANTS, TEMPORARY VARIABLES
'=========================================================================================================
' Alias pins


'=========================================================================================================
' Variables
'=========================================================================================================
a   var byte                    ' Loop counter. 
b var byte[8]
'=========================================================================================================
' Constants
'=========================================================================================================
 
' -----[ Initialization ]---------------------------------------------------------------- 


'    Clear                       ' Reset all variables.


	INCLUDE "modedefs.bas"		' Include serial modes.
	
    DEFINE DEBUG_REG PORTC      ' Debug pin port.
    DEFINE DEBUG_BIT 3          ' Debug pin.
    DEFINE DEBUG_BAUD 9600      ' Debug baud rate
    DEFINE DEBUG_MODE 1         ' Debug mode: 0 = True, 1 = Inverted
'    DEFINE DEBUG_PACING 1000    ' Debug character pacing in us
    DEFINE DEBUGIN_BIT 4        ' Input pin.


    DEFINE  OSC 4               ' Adjust to suit design.
    OSCCON  = %01101011         ' Internal 4MHz osc.
'    OSCCON  = %01110011         ' Internal 8MHz osc.
'    OSCCON  = %01111011         ' Internal 16MHz osc.
'    OSCCON  = %11110011         ' Internal 32MHz osc PLL.


    OPTION_REG.7 = 1            ' Disable weak pullups.
'    OPTION_REG.7 = 0            ' Enable weak pullups.


'    DEFINE ADC_BITS 10          ' Set number of bits in result.
'    DEFINE ADC_CLOCK 3          ' Set clock source (rc = 3).
'    DEFINE ADC_SAMPLEUS 50      ' Set sampling time in microseconds. 


    ADCON0 = 0                  ' No ADC.
'    ADCON0 = %00000001          ' Enable ADC.
'    ADCON1 = %10000000          ' Right justify, Frc, use Vdd for Vref.
'    ADCON2 = %00000000          ' No Trigger selects.


    ANSELA = 0                  ' Disable ADC.
'    ANSELA = %00000100          ' AN2 the rest Dig.
    ANSELC = %00000000          ' All Dig.


    CM1CON0 = 0                  ' Comparators off.


'    FVRCON = %0                 ' Disabled.
    FVRCON = %11000101          ' Enabled, Vref 1.024V.
'    DAC1CON0 = %10101000        ' Vref from FVR, DAC1out1 (RA0).
'=========================================================================================================
' ####### RA2 Sits at 2.277V with RA0 selected and running correctly.
    DAC1CON0 = %10010000        ' Vref from FVR, DAC1out2 (RA2).  
'=========================================================================================================
'    DAC1CON0 = %10111000        ' Vref from FVR, both outputs (RA0, RA2).  [Not sure if this is possible]
    DAC1CON1 = %10000000        ' Set initial output value to 50% of Vref.


    TRISA = %000000             ' All output.
    TRISC = %010100             ' C.4 serial in.


    latC.3 = 0                  ' Else first serial chars can be garbled...
    Pause 1000					' Short wait for things to settle.
debug "I'm Alive!", 13,10       ' Eureka moment.
    pause 3000                  ' Time enough to gloat.
    
   b[0]=128
   b[1]=192
   b[2]=255
   b[3]=192
   b[4]=128
   b[5]=40
   b[6]=0
   b[7]=40
'=========================================================================================================
' Subroutines
'=========================================================================================================


'=========================================================================================================
' Main
'=========================================================================================================
First:  
    a=7
    while a
    DAC1CON1 = b[a]
;debug "DAC = ",#a,13,10     ' 
    pause 5            ' Let the DMM settle.
    a=a-1
    wend
    goto first              ' Cycle.


    end
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