Controlling OG-4 Decathron with PBP in an efficient way.


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  1. #1
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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    Run into strange problem - setting GPIO.5 as input messes with GPIO.4 - it becomes high when GPIO.5 is read, so disrupts complete code routine. I'm using TRISIO=%00100000 to make GPIO.5 as input. If I disable it as input, then other code works fine.

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    In your code at the top of the page you list TRISIO=%00001000. Of course GPIO.3 is MCLR and is Input only. In the previous post you state you are having problems with TRISIO=%00100000. It's probably not your issue, but try TRISIO=%00101000.

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    It does not helps. And I'm not using MCLR pin for anything except programming. Tried TRISIO=%00101000 but that does not helps. Tried disabling MCLR from config, also no change. Making a pin input creates issues with others being output.

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    Did you try a new PIC? I've never seen what you're describing. Thinking something internal might be whacked.

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    its a classic rmw problem.
    can also be caused by excessive load on output pin (capacitive or resitive) causing pin to not achieve proper logic level.
    Warning I'm not a teacher

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    Yes tried new chip. Output pins are connected to MPSA42 transistor via 10K resistor.

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    If I swap chip with 12F1840, will problem still exist?

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    Default Re: Controlling OG-4 Decathron with PBP in an efficient way.

    I tried to replace HIGH/LOW statements with TRISIO.X=1 or 0, it does not helps. In fact, say TRISIO.0=1 does not make GPIO.0 pin high.

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