I'm not sure the config strings are right. After looking at the .INC file in MPLABX it says the config bits are to be constructed such as:

;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0'; LP oscillator
_OSC_XT_1H EQU H'F1'; XT oscillator
_OSC_HS_1H EQU H'F2'; HS oscillator
_OSC_RC2_1H EQU H'F3'; External RC oscillator, CLKO function on RA6
_OSC_EC_1H EQU H'F4'; EC oscillator, CLKO function on RA6
_OSC_ECIO_1H EQU H'F5'; EC oscillator, port function on RA6
_OSC_HSPLL_1H EQU H'F6'; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
_OSC_RCIO_1H EQU H'F7'; External RC oscillator, port function on RA6
_OSC_IRCIO_1H EQU H'F8'; Internal oscillator block, port function on RA6 and port function on RA7
_OSC_IRC_1H EQU H'F9'; Internal oscillator block, CLKO function on RA6 and port function on RA7
_OSC_RC1_1H EQU H'FA'; 101X External RC oscillator, CLKO function on RA6
_OSC_RC_1H EQU H'FC'; 11XX External RC oscillator, CLKO function on RA6

_FCMEN_OFF_1H EQU H'BF'; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF'; Fail-Safe Clock Monitor enabled

_IESO_OFF_1H EQU H'7F'; Internal External Switchover mode disabled
_IESO_ON_1H EQU H'FF'; Internal External Switchover mode enabled

;----- CONFIG2L Options --------------------------------------------------
_PWRTEN_ON_2L EQU H'FE'; PWRT enabled
_PWRTEN_OFF_2L EQU H'FF'; PWRT disabled

_BOREN_OFF_2L EQU H'FD'; Brown-out Reset disabled
_BOREN_ON_2L EQU H'FF'; Brown-out Reset enabled

_BORV_45_2L EQU H'F3'; VBOR set to 4.5V
_BORV_42_2L EQU H'F7'; VBOR set to 4.2V
_BORV_27_2L EQU H'FB'; VBOR set to 2.7V
_BORV_20_2L EQU H'FF'; Reserved

;----- CONFIG2H Options --------------------------------------------------
_WDTEN_OFF_2H EQU H'FE'; WDT disabled (control is placed on the SWDTEN bit)
_WDTEN_ON_2H EQU H'FF'; WDT enabled

_WDPS_1_2H EQU H'E1'; 1:1
_WDPS_2_2H EQU H'E3'; 1:2
_WDPS_4_2H EQU H'E5'; 1:4
_WDPS_8_2H EQU H'E7'; 1:8
_WDPS_16_2H EQU H'E9'; 1:16
_WDPS_32_2H EQU H'EB'; 1:32
_WDPS_64_2H EQU H'ED'; 1:64
_WDPS_128_2H EQU H'EF'; 1:128
_WDPS_256_2H EQU H'F1'; 1:256
_WDPS_512_2H EQU H'F3'; 1:512
_WDPS_1024_2H EQU H'F5'; 1:1024
_WDPS_2048_2H EQU H'F7'; 1:2048
_WDPS_4096_2H EQU H'F9'; 1:4096
_WDPS_8192_2H EQU H'FB'; 1:8192
_WDPS_16384_2H EQU H'FD'; 1:16384
_WDPS_32768_2H EQU H'FF'; 1:32768

_WINEN_ON_2H EQU H'DF'; WDT window enabledbled
_WINEN_OFF_2H EQU H'FF'; WDT window disabled

;----- CONFIG3L Options --------------------------------------------------
_PWMPIN_ON_3L EQU H'FB'; PWM outputs drive active states upon Reset
_PWMPIN_OFF_3L EQU H'FF'; PWM outputs disabled upon Reset (default)

_LPOL_LOW_3L EQU H'F7'; PWM0, 2, 4 and 6 are active-low
_LPOL_HIGH_3L EQU H'FF'; PWM0, 2, 4 and 6 are active-high

_HPOL_LOW_3L EQU H'EF'; PWM1, 3, 5 and 7 are active-low
_HPOL_HIGH_3L EQU H'FF'; PWM1, 3, 5 and 7 are active-high

_T1OSCMX_OFF_3L EQU H'DF'; Standard (legacy) Timer1 oscillator operation
_T1OSCMX_ON_3L EQU H'FF'; Low-power Timer1 operation when microcontroller is in Sleep mode

;----- CONFIG3H Options --------------------------------------------------
_FLTAMX_RD4_3H EQU H'FE'; FLTA input is multiplexed with RD4
_FLTAMX_RC1_3H EQU H'FF'; FLTA input is multiplexed with RC1

_SSPMX_RD1_3H EQU H'FB'; SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1.
_SSPMX_RC7_3H EQU H'FF'; SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7.

_PWM4MX_RD5_3H EQU H'F7'; PWM4 output is multiplexed with RD5
_PWM4MX_RB5_3H EQU H'FF'; PWM4 output is multiplexed with RB5

_EXCLKMX_RD0_3H EQU H'EF'; TMR0/T5CKI external clock input is multiplexed with RD0
_EXCLKMX_RC3_3H EQU H'FF'; TMR0/T5CKI external clock input is multiplexed with RC3

_MCLRE_OFF_3H EQU H'7F'; Disabled
_MCLRE_ON_3H EQU H'FF'; Enabled

;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE'; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF'; Stack full/underflow will cause Reset

_LVP_OFF_4L EQU H'FB'; Low-voltage ICSP disabled
_LVP_ON_4L EQU H'FF'; Low-voltage ICSP enabled

_DEBUG_ON_4L EQU H'7F'; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF'; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins

;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE'; Block 0 (000200-000FFFh) code-protected
_CP0_OFF_5L EQU H'FF'; Block 0 (000200-000FFFh) not code-protected

_CP1_ON_5L EQU H'FD'; Block 1 (001000-001FFF) code-protected
_CP1_OFF_5L EQU H'FF'; Block 1 (001000-001FFF) not code-protected

_CP2_ON_5L EQU H'FB'; Block 2 (002000-002FFFh) code-protected
_CP2_OFF_5L EQU H'FF'; Block 2 (002000-002FFFh) not code-protected

_CP3_ON_5L EQU H'F7'; Block 3 (003000-003FFFh) code-protected
_CP3_OFF_5L EQU H'FF'; Block 3 (003000-003FFFh) not code-protected

;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF'; Boot Block (000000-0001FFh) code-protected
_CPB_OFF_5H EQU H'FF'; Boot Block (000000-0001FFh) not code-protected

_CPD_ON_5H EQU H'7F'; Data EEPROM code-protected
_CPD_OFF_5H EQU H'FF'; Data EEPROM not code-protected

;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE'; Block 0 (000200-000FFFh) write-protected
_WRT0_OFF_6L EQU H'FF'; Block 0 (000200-000FFFh) not write-protected

_WRT1_ON_6L EQU H'FD'; Block 1 (001000-001FFF) write-protected
_WRT1_OFF_6L EQU H'FF'; Block 1 (001000-001FFF) not write-protected

_WRT2_ON_6L EQU H'FB'; Block 2 (002000-002FFFh) write-protected
_WRT2_OFF_6L EQU H'FF'; Block 2 (002000-002FFFh) not write-protected

_WRT3_ON_6L EQU H'F7'; Block 3 (003000-003FFFh) write-protected
_WRT3_OFF_6L EQU H'FF'; Block 3 (003000-003FFFh) not write-protected

;----- CONFIG6H Options --------------------------------------------------
_WRTC_ON_6H EQU H'DF'; Configuration registers (300000-3000FFh) write-protected
_WRTC_OFF_6H EQU H'FF'; Configuration registers (300000-3000FFh) not write-protected

_WRTB_ON_6H EQU H'BF'; Boot Block (000000-0001FFh) write-protected
_WRTB_OFF_6H EQU H'FF'; Boot Block (000000-0001FFh) not write-protected

_WRTD_ON_6H EQU H'7F'; Data EEPROM write-protected
_WRTD_OFF_6H EQU H'FF'; Data EEPROM not write-protected

;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE'; Block 0 (000200-000FFFh) protected from table reads executed in other blocks
_EBTR0_OFF_7L EQU H'FF'; Block 0 (000200-000FFFh) not protected from table reads executed in other blocks

_EBTR1_ON_7L EQU H'FD'; Block 1 (001000-001FFF) protected from table reads executed in other blocks
_EBTR1_OFF_7L EQU H'FF'; Block 1 (001000-001FFF) not protected from table reads executed in other blocks

_EBTR2_ON_7L EQU H'FB'; Block 2 (002000-002FFFh) protected from table reads executed in other blocks
_EBTR2_OFF_7L EQU H'FF'; Block 2 (002000-002FFFh) not protected from table reads executed in other blocks

_EBTR3_ON_7L EQU H'F7'; Block 3 (003000-003FFFh) protected from table reads executed in other blocks
_EBTR3_OFF_7L EQU H'FF'; Block 3 (003000-003FFFh) not protected from table reads executed in other blocks

;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF'; Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
_EBTRB_OFF_7H EQU H'FF'; Boot Block (000000-0001FFh) not protected from table reads executed in other blocks

I'm not sure any of them are being set correctly. Here is an example for a project I did some time ago:

#CONFIG
;----- CONFIG1H Options --------------------------------------------------
__config _CONFIG1H, _FOSC_INTIO7_1H & _PLLCFG_ON_1H & _PRICLKEN_ON_1H & _FCMEN_ON_1H & _IESO_OFF_1H
;----- CONFIG2L Options --------------------------------------------------
__config _CONFIG2L, _PWRTEN_ON_2L & _BOREN_ON_2L & _BORV_190_2L
;----- CONFIG2H Options --------------------------------------------------
__config _CONFIG2H, _WDTEN_OFF_2H & _WDTPS_32768_2H
;----- CONFIG3H Options --------------------------------------------------
__config _CONFIG3H, _CCP2MX_PORTB3_3H & _PBADEN_OFF_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _MCLRE_EXTMCLR_3H
;----- CONFIG4L Options --------------------------------------------------
__config _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
#ENDCONFIG

This is the syntax I use ...