Quote Originally Posted by richard View Post
yes , any software timed process can be adversely affected by the huge overhead imposed by a dt int style pbp interrupt.
there are many solutions :-
in no particular order
1. lower the baud rate till errors minimised
2. disable interrupt during transmission
3. run chip at 64mhz to minimise isr latency
4. use the eusart
5. send 1 chr at a time with isr disabled to minimise "lost" interrupts
Richard,
I suspected so and thanks for the great tips! Which raises another question: so the end goal was to run the DT elapsed timer in the background for another application (same chip) with lots of processing going on (constant I2C sensor acquisition from 2 devices, EEPROM writing, constant A>D conversion, a fair chunk of numerical processing). So, there's no serial comms during this, but lots happening, so is it likely to expect the elapsed timer to corrupt some of this processing or acquisition? - I'm using PBP3's I2C commands for the I2C comms but doing the A>D acquisition via direct register access.

Thanks again,

Troy