First, you get a PIR0.4 generic IOCIF that's read only. Second, you also get an IOCAF/IOCBF/IOCCF.PortPin flag that indicates either an IOCAN or IOCAP type flag (since you can use either). the PIR0.4 flag automatically clears when IOCxFs = 0. With that said, you can clear the flag manually in the ISR. If you got IOCAF.2 (RA2 changed state according to your IOCAP/IOCAN Registers), at the end of your ISR add IOCAF.2 = 0 (PBP3). If you are using an ASM ISR, BCF IOCAF,2.

"16.1 Enabling the Module
To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated."

That being said, we're getting more familiar with how the K40 chip & Data Sheet don't always agree. You could clear the IOCxN/P in the Register to disable IOCIE if PIE0.4 = 0 fails to work.