Normal i/o required on portc , pin6, 7 18f27k40

[longpole001]

Hi guys , wondering if anyone has config set the normal port c i/o pins 6, 7 for the 18f27k40 , as it appears to not respond ,

the portc pins 6,7 can be used as Usart1 , but i require it to be standard i/o


here what i have that effects port c

  '  -------   Port C Settings & directions  ----------
    ANSELC  = %00000000          ' Set Port C Analog bit7-0 = ANC7-0 / 0 = digital ,1= Analog   
    TRISC   = %00000100          ' 1= Digital Input / 0= Digital Outputs  ANC7 = spare_tx1 output when IR-TX
    IOCCN   = %00000000          ' IOC Negative Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    WPUC    = %00000000          ' Set Week Pullups on Digital inputs POR =0  
    INLVLC  = %11111111          ' Set Input levels - Schmitt = 1 / TTL = 0  POR = 1 
    SLRCONC = %11111111          ' Set Slew Rate 1 = Rate Limited  0 = Max rate POR =1 
    IOCCP   = %00000000          ' IOC Positive Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    ODCONC  = %00000000          ' Open Drain 0 = Output drives both High and Low signals  1= Output drives Low going signals only POR = 0
    

   PMD4 = %01111111	'Bit7= UART2, Bit6= UART1, Bit5= MSSP2 , Bit4=MSSP1,Bit3-1 =N/A , Bit0= CWG1 ( Comparitor Output shutdown )

[mpgmike]

 PPSLOCK    =   $55                 ;PPS Unlock Sequence
 PPSLOCK    =   $AA
 PPSLOCK    =   0
RC6PPS = 0
RC7PPS = 0
 PPSLOCK    =   $55                 ;PPS Lock Sequence
 PPSLOCK    =   $AA
 PPSLOCK    =   1

[longpole001]

thanks mike ill give that ago ,


i have not locked down pps at any point so i should not need to unlock it , from what i currenlty understand of the k40 series

[Dave]

That is right Sheldon, But you do initially have to unlock the PPS register. It's up to you to lock it after or as I do, leave it unlocked so as to make later changes to it.

[tumbleweed]

You shouldn't have to make any changes to the PPS registers or the PPSLOCK unless you've done something to change them.

The PPSLOCK powers up as unlocked, and the PORT pins default to the PORT data latch (no PPS in effect at reset).

PORTC should work after setting up the TRISC and ANSELC registers.

[Dave]

Yes Sheldon, Tumbleweed is right, as long as " CONFIG PPS1WAY = OFF " is set in this way at processor configuration. All "RxyPPS pins default to the "LATxy" upon "POR". However peripherals inputs default to the states listed in section 17.1 of the data sheet.

[tumbleweed]

Dave, I think the PPS1WAY config bit only controls whether or not you can change the PPSLOCK bit once you've written to it to set it.

If you never lock the pps in the first place then you don't need to unlock it, so that setting shouldn't matter.

[longpole001]

hi dave

well setting
RC6PPS = 0
RC7PPS = 0

allowed the pins to work as I/O on portc pins6,7, in this case both pins are outputs
prior to the above command both pins were high by default and only dipped 0.7v when asked to change to a low state , which made me consider they were acting as usart1 pins


I did not have to unlock the pps
i have not set the lock pps bit in the config

also PMD4 - Usart was not active , but still the pins were effected , but thats not a big surprise

so what other PPS port pins need to be set to 0 on each port before they can be used as standard i/o , clearly not all as other port pins have responded as expected from TRIS, perhasp is it is just the USART's ???

or should the standard approach for each port be ,to set RxyPPS = 0 , done in each port section, and only changed from 0 / command removed when a PPS fuction is required on those pins

table 17.1. at POR shows for PPS inputs port pins , this appears to override TRIS settings until RxyPPS = 0 is set , thus allowing TRIS standard i/o of those pins ???

If table 17.2 has no POR for outputs , then i should not need to to do RxyPPS = 0 before the port worked as standard I/O , but clearly i needed to do it so that USART1 was not effected on portc,pin6, 7 ?

a little confusing

cheers

Sheldon

[tumbleweed]

I'm staring at a 27K40.

I have config PPS1WAY off.

No pps, no nothing but:

trisc.7 = 0
portc.7 = 1
portc.7 = 0

trisc.6 = 0
portc.6 = 1
portc.6 = 0

and the pins go high and low for me.

[longpole001]

hi tumbleweed, i will look further

but here is what i have , which i agree with you PPS should not effect portC with the config i have

but i without the RC6pps =0 ,RC7PPS= 0 the pins are definitely not responding as i/o pins

I have silicon 0 sample from microchip btw , but that should not be a factor

at time of testing the pins dont have any other components connected to outputs except a cro

 
' config for 18F27K40
 
    #CONFIG

;----- CONFIG1L Options --------------------------------------------------
    CONFIG FEXTOSC   = OFF	           ; External Oscillator not enabled
    CONFIG RSTOSC    = HFINTOSC_64MHZ  ; HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1 

;----- CONFIG1H Options --------------------------------------------------
    CONFIG CLKOUTEN  = OFF	           ; CLKOUT function is disabled I/O fuction on OSC2
    CONFIG CSWEN     = ON	           ; Writing to NOSC and NDIV is allowed ( software can change OSC type and speed as required after POR)
    CONFIG FCMEN     = OFF	           ; Fail-Safe Clock Monitor disabled 
   
;----- CONFIG2L Options --------------------------------------------------
    CONFIG MCLRE     = EXTMCLR	       ; If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is input - used a s reset by CCT
    CONFIG PWRTE     = ON	           ; Power up timer enabled - provides 66ms timeout on POR or Brown out reset 
    CONFIG LPBOREN   = OFF	           ; LPBOR disabled  ( Low Power Brown Out Reset disabled)
    CONFIG BOREN     = ON	           ; Brown-out Reset Enabled according to SBOREN
   
;----- CONFIG2H Options --------------------------------------------------
    CONFIG BORV      = VBOR_245	       ; Brown-out Reset Voltage (VBOR) set to 2.45V
    CONFIG ZCD       = OFF	           ; ZCD disabled. Zero Cross Detect can be enabled by setting the ZCDSEN bit of ZCDCON
    CONFIG PPS1WAY   = OFF	           ; PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
    CONFIG STVREN    = ON	           ; Stack full/underflow will cause Reset
    CONFIG DEBUG     = OFF	           ; Background debugger disabled
    CONFIG XINST     = OFF	           ; Extended Instruction Set and Indexed Addressing Mode disabled

;----- CONFIG3L Options --------------------------------------------------
    CONFIG WDTCPS    = WDTCPS_31	   ; Divider ratio 1:65536; software control of WDTPS
    CONFIG WDTE      = OFF	           ; WDT Disabled -  Watch Dog Timer disabled                    

;----- CONFIG3H Options --------------------------------------------------
    CONFIG WDTCWS    = WDTCWS_7	       ; window always open (100%); software control; keyed access not required
    CONFIG WDTCCS    = LFINTOSC	       ; WDT reference clock is the 31.0 kHz LFINTOSC
 
;----- CONFIG4L Options --------------------------------------------------
    CONFIG WRT0      = OFF	           ; Block 0 (000800-003FFFh) not write-protected
    CONFIG WRT1      = OFF	           ; Block 1 (004000-007FFFh) not write-protected
    CONFIG WRT2      = OFF	           ; Block 2 (008000-00BFFFh) not write-protected
    CONFIG WRT3      = OFF	           ; Block 3 (00C000-00FFFFh) not write-protected
    CONFIG WRT4      = OFF	           ; Block 4 (010000-013FFFh) not write-protected
    CONFIG WRT5      = OFF	           ; Block 5 (014000-017FFFh) not write-protected
    CONFIG WRT6      = OFF	           ; Block 6 (018000-01BFFFh) not write-protected
    CONFIG WRT7      = OFF	           ; Block 7 (01C000-01FFFFh) not write-protected

;----- CONFIG4H Options --------------------------------------------------
    CONFIG WRTC      = OFF	           ; Configuration registers (300000-30000Bh) not write-protected
    CONFIG WRTB      = OFF	           ; Boot Block (000000-0007FFh) not write-protected
    CONFIG WRTD      = OFF	           ; Data EEPROM not write-protected
    CONFIG SCANE     = ON	           ; Scanner module is available for use, SCANMD bit can control the module
    CONFIG LVP       = OFF	           ; HV on MCLR/VPP must be used for programming

;----- CONFIG5L Options --------------------------------------------------  
    CONFIG CP        = OFF	           ; UserNVM code protection disabled
    CONFIG CPD       = OFF	           ; DataNVM code protection disabled
   
;----- CONFIG5H Options --------------------------------------------------  
; not used   
  
;----- CONFIG6L Options --------------------------------------------------  
   CONFIG EBTR0      = OFF	          ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR1      = OFF	          ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR2      = OFF	          ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR3      = OFF	          ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR4      = OFF	          ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR5      = OFF	          ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR6      = OFF	          ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR7      = OFF	          ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
  
;----- CONFIG6H Options --------------------------------------------------  
   CONFIG EBTRB      = OFF	          ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks

 
   #ENDCONFIG

' ----------------  Setup All Define statements ------------ 
    DEFINE OSC 32               ' Timing referance for pause , pauseus commands
    DEFINE ADC_BITS 10          ' Number of bits in ADCIN result - Required for adcin command 
    DEFINE PULSIN_MAX 2000      ' Maximum counts( clock ticks) allowed before pulsin times out( 2000 ^ 1.25us =  2.5 ms)
    DEFINE HSER_PORT 2          ' Hser port 2 use 
    DEFINE HSER2_RXREG PORTB    ' USART 2 RX - Set PPS Register port B
    DEFINE HSER2_RXBIT 7        ' 
    DEFINE HSER2_TXREG PORTB
    DEFINE HSER2_TXBIT 6
    DEFINE HSER2_RCSTA 90h      ' Hser2 receive status init
    DEFINE HSER2_TXSTA 24h      ' Hser2 transmit status init
    DEFINE HSER2_BAUD 19200     ' Hser2 baud rate

 '---------------- PERIPHERAL PIN SELECT MODULE -----------------------

    RC6PPS = 0
    RC7PPS = 0
 
'---------------- PERIPHERAL MODULE DISABLE -----------------------
'   Note Bit value 0 = ENABLE , 1 = DISABLED   POR = 0 

	PMD0 = %00111010	'Bit7-Sys clock(Fosc) to Peripherals , Bit6 FVRMD -Fixed Voltage Ref Module  
                        'Bit5 - HLVD Module, Bit4- CRCMD - CRC Module  
                        'Bit3 - SCANMD - NVM Memory Scanner Module , Bit2- NVMMD -NVM module 	
                        'Bit1 - CLKR - Clock Referance , Bit0 IOCMD 
    
    PMD1 = %11111100	'Bit7=N/A ,Bit6=TMR6 ,Bit5=TMR5,Bit4=TMR4,
                        'Bit3=TMR3,Bit2=TMR2,Bit1=TMR1,Bit0=TMR0
	
    PMD2 = %11011111	'Bit7=N/A ,Bit6=DAC ,Bit5=ADC , Bit4=N/A, Bit3=N/A, Bit2= CMP2, Bit1=CMP1,Bit0=ZCD Zero Cross Detect
	
    PMD3 = %11111111	'Bit7-4=N/A, Bit3=PWM4, Bit2=PWM3, Bit1=CCP2, Bit0=CCP1
    
    PMD4 = %01111111	'Bit7= UART2, Bit6= UART1, Bit5= MSSP2 , Bit4=MSSP1,Bit3-1 =N/A , Bit0= CWG1 ( Comparitor Output shutdown )
	PMD5 = %11111111	'Bit7-1= N/A , Bit0 = DSM (Data Signal Module)

  '  -------   Port C Settings & directions  ----------
    ANSELC  = %00000000          ' Set Port C Analog bit7-0 = ANC7-0 / 0 = digital ,1= Analog   
    TRISC   = %00000100          ' 1= Digital Input / 0= Digital Outputs  ANC7 = spare_tx1 output when IR-TX
    IOCCN   = %00000000          ' IOC Negative Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    WPUC    = %00000000          ' Set Week Pullups on Digital inputs POR =0  
    INLVLC  = %11111111          ' Set Input levels - Schmitt = 1 / TTL = 0  POR = 1 
    SLRCONC = %11111111          ' Set Slew Rate 1 = Rate Limited  0 = Max rate POR =1 
    IOCCP   = %00000000          ' IOC Positive Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    ODCONC  = %00000000          ' Open Drain 0 = Output drives both High and Low signals  1= Output drives Low going signals only POR = 0
    
  ' -------   Setup port C Variables  ----------
    SCK           VAR LATC.0       ' Clock pin (output to RF modual)
    SI            Var LATC.1       ' Master Out  - Module Data in pin       (input  to RF Modual)
    SO            Var PORTC.2      ' Master In   - Module Data out pin      (output of RF Modual)
    FLASH1_CE     con 19'= LATC.3  ' Chip select FLASH chip ( low) 
    BUZ           var LATC.4       ' Buzzer 
   IR_TX_OUT     VAR LATC.5        ' IR-TX_out  when IR-TX   
   IR_TX_HI_PWR  VAR LATC.6        ' IR_TX_HI when IR-TX
   SPARE_TX1     VAR LATC.7        ' spare Output when IR_TX mode 
      
    
   LATA.0[FLASH1_CE] = 1      ' Active Low so set High to start

[tumbleweed]

FWIW, the chip I ran that simple example on was rev A2 silicon.

   FLASH1_CE     con 19'= LATC.3  ' Chip select FLASH chip ( low) 
   LATA.0[FLASH1_CE] = 1      ' Active Low so set High to start

This isn't your problem here, but I'd be careful using that syntax to access a bit in LATC.
I've seen chips where the LATx (and other port related regs) aren't contiguous in memory so that would fail.

[towlerg]

FWIW Microchip have changed the format of device/siliocon rev for 10F2xK40/42, so watch out for that. These devices are quite new so the errata may not be complete, I see no downside in setting up the PPS of all the pins you are going to use, whether it's necessay or not.

[longpole001]

yes i checked that the lat registers were contiguous so use the offset works fine

i am thinking that the devices that use bi direction pins such as usarts , need the PPS set to be off if those services are not in use ,

it not harm anything if i set all pins not requiring a pps service to 0 as it clear makes them i/o use regardless

[longpole001]

another thing to note on the 2xk40 ,4xK40 , is that usart 2 default pins share the ISCP pins

although notes on PBP3.1.1 for the k40 indicate a possible ISCP lockout can occur , i have not had this happen

what i have found is that while programing using iscp , with the terminal port connected , which also provides alt power to my device , the device driver for the usb to ttl chip can occasionally hang the pc while the ISCP is programing

so i would recommend allocating other pins for usart2 when designing with k40 , if you ever need the ISCP port ,

the k40 PPS port make it nice to do this

charles recommends in the notes
RX2 = RB5 on 2xk40, 4x40
TX2 = RB4 on 2xk40 , 4xk40

DEFINE HSER2_RXREG PORTB
DEFINE HSER2_RXBIT 5
DEFINE HSER2_TXREG PORTB
DEFINE HSER2_TXBIT 4



cheers

Sheldon

[Dave]

Sheldon, If you look at the date sheet page 229 you will see that the default pin selection's for USART2 input is on port B.7. I have never in the past 2 or so years had any problem with LOCKOUT of the ICSP. I always use the 2 USART hardware serial ports for my projects. I only have to set the Output PPS port pins for the 2 hardware USART's. I use RC6PPS = 09 and RB6PPS = 0B. I always use a BootLoader as well.

[longpole001]

i will later this coming month start to try and get a bootloader working for the 27k40 , as i really like to get away from iscp programing of chips