hi tumbleweed, i will look further

but here is what i have , which i agree with you PPS should not effect portC with the config i have

but i without the RC6pps =0 ,RC7PPS= 0 the pins are definitely not responding as i/o pins

I have silicon 0 sample from microchip btw , but that should not be a factor

at time of testing the pins dont have any other components connected to outputs except a cro


Code:
 
' config for 18F27K40
 
    #CONFIG

;----- CONFIG1L Options --------------------------------------------------
    CONFIG FEXTOSC   = OFF	           ; External Oscillator not enabled
    CONFIG RSTOSC    = HFINTOSC_64MHZ  ; HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1 

;----- CONFIG1H Options --------------------------------------------------
    CONFIG CLKOUTEN  = OFF	           ; CLKOUT function is disabled I/O fuction on OSC2
    CONFIG CSWEN     = ON	           ; Writing to NOSC and NDIV is allowed ( software can change OSC type and speed as required after POR)
    CONFIG FCMEN     = OFF	           ; Fail-Safe Clock Monitor disabled 
   
;----- CONFIG2L Options --------------------------------------------------
    CONFIG MCLRE     = EXTMCLR	       ; If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is input - used a s reset by CCT
    CONFIG PWRTE     = ON	           ; Power up timer enabled - provides 66ms timeout on POR or Brown out reset 
    CONFIG LPBOREN   = OFF	           ; LPBOR disabled  ( Low Power Brown Out Reset disabled)
    CONFIG BOREN     = ON	           ; Brown-out Reset Enabled according to SBOREN
   
;----- CONFIG2H Options --------------------------------------------------
    CONFIG BORV      = VBOR_245	       ; Brown-out Reset Voltage (VBOR) set to 2.45V
    CONFIG ZCD       = OFF	           ; ZCD disabled. Zero Cross Detect can be enabled by setting the ZCDSEN bit of ZCDCON
    CONFIG PPS1WAY   = OFF	           ; PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
    CONFIG STVREN    = ON	           ; Stack full/underflow will cause Reset
    CONFIG DEBUG     = OFF	           ; Background debugger disabled
    CONFIG XINST     = OFF	           ; Extended Instruction Set and Indexed Addressing Mode disabled

;----- CONFIG3L Options --------------------------------------------------
    CONFIG WDTCPS    = WDTCPS_31	   ; Divider ratio 1:65536; software control of WDTPS
    CONFIG WDTE      = OFF	           ; WDT Disabled -  Watch Dog Timer disabled                    

;----- CONFIG3H Options --------------------------------------------------
    CONFIG WDTCWS    = WDTCWS_7	       ; window always open (100%); software control; keyed access not required
    CONFIG WDTCCS    = LFINTOSC	       ; WDT reference clock is the 31.0 kHz LFINTOSC
 
;----- CONFIG4L Options --------------------------------------------------
    CONFIG WRT0      = OFF	           ; Block 0 (000800-003FFFh) not write-protected
    CONFIG WRT1      = OFF	           ; Block 1 (004000-007FFFh) not write-protected
    CONFIG WRT2      = OFF	           ; Block 2 (008000-00BFFFh) not write-protected
    CONFIG WRT3      = OFF	           ; Block 3 (00C000-00FFFFh) not write-protected
    CONFIG WRT4      = OFF	           ; Block 4 (010000-013FFFh) not write-protected
    CONFIG WRT5      = OFF	           ; Block 5 (014000-017FFFh) not write-protected
    CONFIG WRT6      = OFF	           ; Block 6 (018000-01BFFFh) not write-protected
    CONFIG WRT7      = OFF	           ; Block 7 (01C000-01FFFFh) not write-protected

;----- CONFIG4H Options --------------------------------------------------
    CONFIG WRTC      = OFF	           ; Configuration registers (300000-30000Bh) not write-protected
    CONFIG WRTB      = OFF	           ; Boot Block (000000-0007FFh) not write-protected
    CONFIG WRTD      = OFF	           ; Data EEPROM not write-protected
    CONFIG SCANE     = ON	           ; Scanner module is available for use, SCANMD bit can control the module
    CONFIG LVP       = OFF	           ; HV on MCLR/VPP must be used for programming

;----- CONFIG5L Options --------------------------------------------------  
    CONFIG CP        = OFF	           ; UserNVM code protection disabled
    CONFIG CPD       = OFF	           ; DataNVM code protection disabled
   
;----- CONFIG5H Options --------------------------------------------------  
; not used   
  
;----- CONFIG6L Options --------------------------------------------------  
   CONFIG EBTR0      = OFF	          ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR1      = OFF	          ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR2      = OFF	          ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR3      = OFF	          ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR4      = OFF	          ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR5      = OFF	          ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
   CONFIG EBTR6      = OFF	          ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
   CONFIG EBTR7      = OFF	          ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
  
;----- CONFIG6H Options --------------------------------------------------  
   CONFIG EBTRB      = OFF	          ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks

 
   #ENDCONFIG


Code:
' ----------------  Setup All Define statements ------------ 
    DEFINE OSC 32               ' Timing referance for pause , pauseus commands
    DEFINE ADC_BITS 10          ' Number of bits in ADCIN result - Required for adcin command 
    DEFINE PULSIN_MAX 2000      ' Maximum counts( clock ticks) allowed before pulsin times out( 2000 ^ 1.25us =  2.5 ms)
    DEFINE HSER_PORT 2          ' Hser port 2 use 
    DEFINE HSER2_RXREG PORTB    ' USART 2 RX - Set PPS Register port B
    DEFINE HSER2_RXBIT 7        ' 
    DEFINE HSER2_TXREG PORTB
    DEFINE HSER2_TXBIT 6
    DEFINE HSER2_RCSTA 90h      ' Hser2 receive status init
    DEFINE HSER2_TXSTA 24h      ' Hser2 transmit status init
    DEFINE HSER2_BAUD 19200     ' Hser2 baud rate

Code:
 '---------------- PERIPHERAL PIN SELECT MODULE -----------------------

    RC6PPS = 0
    RC7PPS = 0
 
'---------------- PERIPHERAL MODULE DISABLE -----------------------
'   Note Bit value 0 = ENABLE , 1 = DISABLED   POR = 0 

	PMD0 = %00111010	'Bit7-Sys clock(Fosc) to Peripherals , Bit6 FVRMD -Fixed Voltage Ref Module  
                        'Bit5 - HLVD Module, Bit4- CRCMD - CRC Module  
                        'Bit3 - SCANMD - NVM Memory Scanner Module , Bit2- NVMMD -NVM module 	
                        'Bit1 - CLKR - Clock Referance , Bit0 IOCMD 
    
    PMD1 = %11111100	'Bit7=N/A ,Bit6=TMR6 ,Bit5=TMR5,Bit4=TMR4,
                        'Bit3=TMR3,Bit2=TMR2,Bit1=TMR1,Bit0=TMR0
	
    PMD2 = %11011111	'Bit7=N/A ,Bit6=DAC ,Bit5=ADC , Bit4=N/A, Bit3=N/A, Bit2= CMP2, Bit1=CMP1,Bit0=ZCD Zero Cross Detect
	
    PMD3 = %11111111	'Bit7-4=N/A, Bit3=PWM4, Bit2=PWM3, Bit1=CCP2, Bit0=CCP1
    
    PMD4 = %01111111	'Bit7= UART2, Bit6= UART1, Bit5= MSSP2 , Bit4=MSSP1,Bit3-1 =N/A , Bit0= CWG1 ( Comparitor Output shutdown )
	PMD5 = %11111111	'Bit7-1= N/A , Bit0 = DSM (Data Signal Module)

Code:

  '  -------   Port C Settings & directions  ----------
    ANSELC  = %00000000          ' Set Port C Analog bit7-0 = ANC7-0 / 0 = digital ,1= Analog   
    TRISC   = %00000100          ' 1= Digital Input / 0= Digital Outputs  ANC7 = spare_tx1 output when IR-TX
    IOCCN   = %00000000          ' IOC Negative Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    WPUC    = %00000000          ' Set Week Pullups on Digital inputs POR =0  
    INLVLC  = %11111111          ' Set Input levels - Schmitt = 1 / TTL = 0  POR = 1 
    SLRCONC = %11111111          ' Set Slew Rate 1 = Rate Limited  0 = Max rate POR =1 
    IOCCP   = %00000000          ' IOC Positive Edge Trigger Select RC7-RC0  0 = diabled 1 = enabled POR = 0
    ODCONC  = %00000000          ' Open Drain 0 = Output drives both High and Low signals  1= Output drives Low going signals only POR = 0
    
  ' -------   Setup port C Variables  ----------
    SCK           VAR LATC.0       ' Clock pin (output to RF modual)
    SI            Var LATC.1       ' Master Out  - Module Data in pin       (input  to RF Modual)
    SO            Var PORTC.2      ' Master In   - Module Data out pin      (output of RF Modual)
    FLASH1_CE     con 19'= LATC.3  ' Chip select FLASH chip ( low) 
    BUZ           var LATC.4       ' Buzzer 
   IR_TX_OUT     VAR LATC.5        ' IR-TX_out  when IR-TX   
   IR_TX_HI_PWR  VAR LATC.6        ' IR_TX_HI when IR-TX
   SPARE_TX1     VAR LATC.7        ' spare Output when IR_TX mode 
      
    
   LATA.0[FLASH1_CE] = 1      ' Active Low so set High to start