Re: GPS Project: PIC18F26K22 or PIC18F46K22
Second Question is: How to do we set the configuration fuses for the PIC, especially for the PIC18F26K22?
Right now the first step is to Flash an LED at port RC3 ( pin14 ) of the PIC18F26K22.
The following code is written in order to Flash the LED on the specific port.
For me at the moment is quit difficult to explain the configuration fuses for all the setups, mostly important to the ones setting the frequency at high external speed HS of 64Mhz.
From the manual it says that we need to enable the PLL bit and also specify that we are going to use the external OSC.
I might need the help of the ones are most expirienced to help me out regarding the setting for 64 MHZ with an external crystal 16Mhz.
Code:@ ERRORLEVEL -306 ; this command prevents the compiler to give you a notice of * ; crossing page boundary - make sure bits are set * '********************************************************************************* #CONFIG ; The PBP default configuration for the PIC18F26K22 is: ; CONFIG FOSC = RCIO6 ; External RC oscillator CONFIG FOSC = HSHP ; HS oscillator (high power > 16 MHz) ; CONFIG FOSC = INTIO67 ; Internal oscillator block ; CONFIG PLLCFG = ON ; Oscillator used directly CONFIG PRICLKEN = ON ; Primary clock can be disabled by software CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled CONFIG IESO = OFF ; Oscillator Switchover mode disabled CONFIG PWRTEN = OFF ; Power up timer disabled CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled) ; CONFIG BORV = 190 ; VBOR set to 1.90 V nominal ;*--------------------------------------------------------------------------------------------------------;| CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect ;| CONFIG WDTPS = 32768 ; 1:32768 ---> HERE enable the watchdog timer with a 1:32768 postscale ;| ;*--------------------------------------------------------------------------------------------------------;| ; CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1 ; CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset ; CONFIG CCP3MX = PORTB5 ; P3A/CCP3 input/output is multiplexed with RB5 CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status ; CONFIG T3CMX = PORTC0 ; T3CKI is on RC0 ; CONFIG P2BMX = PORTB5 ; P2B is on RB5 CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled ; CONFIG STVREN = ON ; Stack full/underflow will cause Reset CONFIG LVP = OFF ; Single-Supply ICSP disabled CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) CONFIG DEBUG = OFF ; Disabled ;*----------------------------------------------------------------------------------| ;*---------------Available configuration settings for PIC18F26K22-------------------| ;*----------------------------------------------------------------------------------| ; ; Oscillator Selection bits ; CONFIG FOSC = RC ;111X External RC oscillator, CLKOUT function on RA6 ; CONFIG FOSC = ECLPIO6 ;EC oscillator (low power, <500 kHz) ; CONFIG FOSC = ECLP ;EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz) ; CONFIG FOSC = ECMPIO6 ;EC oscillator (medium power, 500 kHz-16 MHz) ; CONFIG FOSC = ECMP ;EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz) ; CONFIG FOSC = INTIO7 ;Internal oscillator block, CLKOUT function on OSC2 ; CONFIG FOSC = INTIO67 ;Internal oscillator block ; CONFIG FOSC = RCIO6 ;External RC oscillator ; CONFIG FOSC = RC ;External RC oscillator, CLKOUT function on OSC2 ; CONFIG FOSC = ECHPIO6 ;EC oscillator (high power, >16 MHz) ; CONFIG FOSC = ECHP ;EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) ; CONFIG FOSC = HSMP ;HS oscillator (medium power 4-16 MHz) ; CONFIG FOSC = HSHP ;HS oscillator (high power > 16 MHz) ; CONFIG FOSC = XT ;XT oscillator ; CONFIG FOSC = LP ;LP oscillator ; ;*------------------------------------------------------------------------------------*| ;* *| ;*---------------------------------4x PLL ENABLE--------------------------------------*| ;* *| ;*------------------------------------------------------------------------------------*| ;* *| ;* 4X PLL Enable *| ;* CONFIG PLLCFG = OFF ;Oscillator used directly *| CONFIG PLLCFG = ON ;Oscillator multiplied by 4 *| ;* *| ;*------------------------------------------------------------------------------------*| ; ; Primary clock enable bit ; CONFIG PRICLKEN = OFF ;Primary clock can be disabled by software ; CONFIG PRICLKEN = ON ;Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit ; CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled ; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit ; CONFIG IESO = OFF ;Oscillator Switchover mode disabled ; CONFIG IESO = ON ;Oscillator Switchover mode enabled ;*--------------------------------------------------------------------------------------------------------| ;* | -------------------------- | | ;* ----------------------------- | [PROTECTED OPTION FUSES] | ------------------------------------ | ;* | -------------------------- | | ;*--------------------------------------------------------------------------------------------------------| CONFIG CP0 = OFF ; Block 0 (000800-003FFFh) not code-protected CONFIG CP1 = OFF ; Block 1 (004000-007FFFh) not code-protected CONFIG CP2 = OFF ; Block 2 (008000-00BFFFh) not code-protected CONFIG CP3 = OFF ; Block 3 (00C000-00FFFFh) not code-protected CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected CONFIG CPD = OFF ; Data EEPROM not code-protected CONFIG WRT0 = OFF ; Block 0 (000800-003FFFh) not write-protected CONFIG WRT1 = OFF ; Block 1 (004000-007FFFh) not write-protected CONFIG WRT2 = OFF ; Block 2 (008000-00BFFFh) not write-protected CONFIG WRT3 = OFF ; Block 3 (00C000-00FFFFh) not write-protected CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ; Data EEPROM not write-protected CONFIG EBTR0 = OFF ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ;*---------------------------------------------------------------------------------------------------------| ;*---------------------------------------------------------------------------------------------------------| #ENDCONFIG define OSC 64 INCLUDE "modedefs.bas" INCLUDE"ALLDIGITAL.pbp" OSCCON = %01110000 ; 64Mhz OSCTUNE.6 = 1 ; Enable 4x PLL LED var PORTC.3 main: high LED pause 10 low LED pause 1000 goto main
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