Logic Probe readings of SCL/SDA lines.
Code:#CONFIG __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF __config _CONFIG5, _CP_OFF & _CPD_OFF #ENDCONFIG DEFINE OSC 32 define CCP1_REG 0 ' Must clear unused CCP pins or else unpredictable results DEFINE CCP1_BIT 0 define CCP2_REG 0 DEFINE CCP2_BIT 0 DEFINE CCP3_REG PORTB DEFINE CCP3_BIT 5 define CCP4_REG 0 DEFINE CCP4_BIT 0 define CCP5_REG 0 DEFINE CCP5_BIT 0 ANSELA = %00000000 ANSELB = %00000000 ANSELC = %00000000 ANSELD = %00000000 ANSELE = %00000000 TRISA = %00000000 TRISB = %00000000 TRISC = %00000000 TRISD = %00000000 TRISE = %00001000 PinSCL2 VAR PortB.1 PinSDA2 VAR PortB.2 HPWM 3, 8, 1953 addr var byte : addr = %01000000 ' $40 IOCONAreg var byte IOCONBreg var byte IODIRAreg var byte IODIRBreg var byte GPIOAreg var byte GPIOBreg var byte IOCONdat var byte IODIRdat var byte GPIOdat var byte IOCONdat = %10110000 ' bit 7 0 = The registers associated with each port are separated into different banks. ' bit 6 0 = The INT pins are not connected. INTA is associated with PORTA and INTB is associated with PORTB ' bit 5 1 = Sequential operation disabled, address pointer does not increment. ' bit 4 1 = Slew rate disabled ' bit 3 0 = Disables the MCP23S17 address pins. ' bit 2 0 = Active driver output (INTPOL bit sets the polarity.) ' bit 1 0 = Active-low ' bit 0 Unimplemented: Read as ‘0’ if IOCONdat.7 = 0 then ' Bank=0 IOCONAreg = $0A IOCONBreg = $0B IODIRAreg = $00 IODIRBreg = $01 GPIOAreg = $12 GPIOBreg = $13 else ' Bank=1 IOCONAreg = $05 IOCONBreg = $15 IODIRAreg = $00 IODIRBreg = $10 GPIOAreg = $09 GPIOBreg = $19 endif IODIRdat = %00000000 'set GPIO all output ' Image 1 I2CWRITE PinSDA2,PinSCL2,addr,[IOCONAreg,IOCONdat] I2CWRITE PinSDA2,PinSCL2,addr,[IODIRAreg,IODIRdat] pause 50 ' Image 2 I2CWRITE PinSDA2,PinSCL2,addr,[IOCONBreg,IOCONdat] I2CWRITE PinSDA2,PinSCL2,addr,[IODIRBreg,IODIRdat] pause 100 LOOOP: ' Image 3 GPIOdat = %00000000 ' LEDs OFF I2CWRITE PinSDA2,PinSCL2,addr,[GPIOAreg,GPIOdat] I2CWRITE PinSDA2,PinSCL2,addr,[GPIOBreg,GPIOdat] pause 200 ' Image 4 GPIOdat = %11111111 ' LEDs ON I2CWRITE PinSDA2,PinSCL2,addr,[GPIOAreg,GPIOdat] I2CWRITE PinSDA2,PinSCL2,addr,[GPIOBreg,GPIOdat] pause 400 GOTO LOOOP end
Image 1:
Image 2:
(next 2 images in next post)
Weird how 2 statements generate 3 groups of pulses (I expected 1 to 1 ratio).





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