Error when compiling with DT_INTS_3_4b"

[Dave]

I have been using the modified DT_INTS_3_4b for some time but, now when I try to use LOW PRIORITY interrupts I get the following ASM ERROR's:
: Illegal character (=)
: Symbol not previously defined (K40 family)

I have been using the 18F27K40 and have now tried to use the 18F47K40 with LOW PRIORITY interrupts.

Code excerpts in order are below:

INCLUDE "C:\PBP\INCLUDES\DT_INTS-18_3_4b.bas" ' Interrupt Control routines
INCLUDE "C:\PBP\INCLUDES\ReEnterPBP-18.bas" ' Interrupt Control routines
INCLUDE "C:\PBP\INCLUDES\ReEnterPBP-18LP.bas" ; Include if using Low Pr. PBP INTS

DEFINE OSC 64
DEFINE USE_LOWPRIORITY 1

asm
;----[High Priority Interrupts]-----------------------------------------------
INT_LIST macro ; IntSource, Label, Type, ResetFlag?
;LINEAR or ROTARY ENCODER INPUT - A (INCREMENT POSITION)
INT_Handler INT0_INT, _INC_C, PBP, yes
;LINEAR or ROTARY ENCODER INPUT - B (DECREMENT POSITION)
INT_Handler INT1_INT, _DEC_C, PBP, yes
endm
INT_CREATE ; Creates the High Priority interrupt processor

;----[Low Priority Interrupts]------------------------------------------------
INT_LIST_L macro ; IntSource, Label, Type, ResetFlag?
INT_Handler TX1_INT, _UARTTX1, PBP, no
INT_Handler RX1_INT, _UARTRX1, PBP, no
INT_Handler TX2_INT, _UARTTX2, PBP, no
INT_Handler RX2_INT, _UARTRX2, PBP, no
INT_Handler TMR1_INT, _TIMR1, PBP, yes
endm
INT_CREATE_L ; Creates the LOW Priority interrupt processor
ENDASM

This coding works perfectly with an 18F26K22 and 18F46K22 before changing to DT_INTS18_3_4b.



Any help would be appreciated...

[tumbleweed]

Dave,

Seems that there were a few mistakes when the low priority interrupts were defined. Try this new version (3.4c) and see if it works out.
It compiled ok using the test code below, but I didn't try actually running it

'18F27K40
DEFINE OSC 64
DEFINE USE_LOWPRIORITY 1

INCLUDE "DT_INTS-18_3_4c.bas" ' Interrupt Control routines
INCLUDE "ReEnterPBP-18.bas"      ' Interrupt Control routines
INCLUDE "ReEnterPBP-18LP.bas"   ' Include if using Low Pr. PBP INTS

GIEH    VAR INTCON.7        ' high priority interrupts
GIEL    VAR INTCON.6        ' low priority interrupts

asm
;----[High Priority Interrupts]-----------------------------------------------
INT_LIST macro ; IntSource, Label, Type, ResetFlag?
    ;LINEAR or ROTARY ENCODER INPUT - A (INCREMENT POSITION)
    INT_Handler INT0_INT, _INC_C, PBP, yes
    ;LINEAR or ROTARY ENCODER INPUT - B (DECREMENT POSITION)
    INT_Handler INT1_INT, _DEC_C, PBP, yes
 endm
    INT_CREATE ; Creates the High Priority interrupt processor

;----[Low Priority Interrupts]------------------------------------------------
INT_LIST_L macro ; IntSource, Label, Type, ResetFlag?
    INT_Handler TX1_INT, _UARTTX1, PBP, no
    INT_Handler RX1_INT, _UARTRX1, PBP, no
    INT_Handler TX2_INT, _UARTTX2, PBP, no
    INT_Handler RX2_INT, _UARTRX2, PBP, no
    INT_Handler TMR1_INT, _TIMER1, PBP, yes
 endm
    INT_CREATE_L ; Creates the LOW Priority interrupt processor
ENDASM

goto OverIntHandlers

INC_C:
@ INT_RETURN

DEC_C:
@ INT_RETURN

UARTTX1:
@ INT_RETURN

UARTRX1:
@ INT_RETURN

UARTTX2:
@ INT_RETURN

UARTRX2:
@ INT_RETURN

TIMER1:
@ INT_RETURN

OverIntHandlers:

'----[ Interrupt control ]-------------------------------------------------------
main:
NOP
GIEL = 1     ' Enable low priority interrupts
GIEH = 1     ' Enable global interrupts

[Dave]

Tumbleweed, It works a treat. Thanks... Wow these K40's can really be a pain but, twice the memory. I only wish my UMC Loader worked with them...

[tumbleweed]

Great. Glad it's working.

I only wish my UMC Loader worked with them...

I've got a 27K40 floating around here someplace. When I get a chance I'll see if I can get a UMC build together that works with it.

[Dave]

I believe the problem is with the UMCBuild.exe file that needs to be changed. I have tried a few times with the config's set for the appropriate devices and all I get is the message "Device not Self Programmable". I have emailed David Barker and he said that he will not support new devices for that Bootloader any more.

[tumbleweed]

UMCBuild.exe requires mpasm and some of the files from the old MPLAB8, but you need mpasmx from MPLABX to support the K40. Add to that it's possible MPLABX no longer includes some of the files UMCBuild is looking for.

I'm pretty sure I can knock something together for you... I just need some free time to look at it.

[tumbleweed]

Well, it turned out that there are so many changes required to get umcbuild to use mpasmx it just wasn't worth the bother.

Here's the asm source for a UMC loader that works with the K40 (at least the 27K40... the only one I tried).
You'll have to change the entries in the USER CONFIGURATION SECTION to match what you're using.
Right now it's setup for an 18F27K40, 16MHz intosc, and uart1 on RC6/RC7.

There are no other files required except for the mpasmx p18FxxK40.inc file. Don't use umcbuild.exe... just assemble it with mpasmx

[Dave]

Thanks Tumbleweed, I will give it a try when I get home from work tonight and let you know.

[Dave]

Well Tumbleweed, I just couldn't wait to try it out. It all looks good. The only error I got when compiling was "undefined symbol":

; check to make sure program fits 26-5-2018
#if $ > DEVICE_ROM
error "program code exceeds flash size. change LOADER_SIZE_MIN"
#endif

I just commented them out and away we go....

Once again, Thanks for the mod's.

[tumbleweed]

The only error I got when compiling was "undefined symbol":

That's odd... I don't get that.

That size check is there to make sure the loader doesn't grow bigger than what's reserved (this one's a bit larger at 512 bytes vs 384).
What version of mpasmx are you using? I was using 5.77

[Dave]

It says, V5.778 in the toolchain. I did notice and have worked on trying to get the bootloader to work with usart2 with no success. I don't understand why?
I have attached the modified version. Maybe if you can, take a look?

[tumbleweed]

All of the control registers for UART1 are in the access bank so you can get away with not using banksel to get to them.
UART2 registers are in a different bank (bank 14, 0x0E99-0x0E9F) so you have to load the BSR (ie BANKSEL RC2STA) to access them.

You can still use UART1 but assign it to different pins with the PPS... that would be a lot easier (and smaller) than adding all the code to get at UART2.

[Dave]

Tumbleweed, I think I will go the ( BANKSEL RC2STA) route because I use the uart1 for different communications to remote arrays. Thanks for the advice, I should have seen that. I am by no means an asm guru but I do know enough to get into trouble.....

[Dave]

Well, This has been a prosperous morning as I have the bootloader running on com2. For this project I need to bootload it over Bluetooth. Thanks so much Tumbleweed for the advice. I can see a whole new future with these K40's.... Thanks...

[longpole001]

hi DAVE

i am also getting some compile errors , that not sure why ,

using DT_INTS-18_34c for the 18F24K40 , no priority is used

  ' ---------- Set up DT_INTS-18 Routine for Instant Interupt handling   -----------
   
     INCLUDE "DT_INTS-18_K40.bas"   ; Base Interrupt System for 18FxxK40 processors  ( DT_INTS-18_3_4C.BAS)
     INCLUDE "ReEnterPBP-18.bas"    ; Include if using PBP interrupts

ASM
INT_LIST macro; IntSource,  Label     , Type, ResetFlag?
   INT_Handler TMR0_INT, _Timer0_Count,  PBP, yes      ; call Timer0_Count subroutine
   INT_Handler  IOC_INT, _Rx_mode_IOC ,  PBP, yes      ; Call Rx_mode_IOC subroutine for RF RX_mode
   INT_Handler  RX2_INT, _Term_RX     ,  PBP, yes      ; Call Term_input for terminal char buffer 
 endm
 INT_CREATE								; Creates the Interrupt Processor
ENDASM

 
--------------------------------------


 '---------- Start of Program commands ---------------
Gate_Reset:                  ' Label for a soft reset 
  Clear                      ' Clear varables    
@ INT_ENABLE TMR0_INT        ; enable Timer0 interupts and start Timer0   
@ INT_ENABLE  IOC_INT        ; Enable PortB IOC Interrupts for RX_mode  - RF_IRQ pin

following compile errors are

 problem - Symbol not previously defined (intflagbit)
 problem - Symbol not previously defined (intflagreg)

; -- macro --
INT_Source  macro  IFR, IFB, IER, IEB, IPR, IPB
    if (IflagReg == IFR) && (IflagBit == IFB)  
  list

error  "INT_ENABLE - Interrupt Source not found!"

[longpole001]

ok found the problem

an include that is common to the project uses enable /disable RBC_INT , which does not exist on the 27k40

hows ever i need to enable/disable RBC_INT when its 46k80 but when its 27k40 use enable/ disable IOC_INT
and want both in the include file

can someone show an example advise how this is done cos i never had to do before

[richard]

4.12 in manual

#IF __PROCESSOR__ = "16F877"
ADCON1 = 7 'All pins digital on the 877A
#ELSE
ANSEL = 0 'AN0-AN7 digital on the 887
ANSELH = 0 'AN8-AN13 digital on the 887
#ENDIF

[mpgmike]

This or some variation may work. I borrowed & modified it from working code.

ASM
#if __PROCESSOR__ = "18F27K40" or __PROCESSOR__ = "18F47K40" 

#define IOC_INT

#else
    #if __PROCESSOR__ = "18F46K80"

#define RBC_INT
#endif
ENDASM

[longpole001]

thanks guys

[longpole001]

hi guys i am trying the low priority interrupts using the int-18_ 3_4c ver on 18f47k40 ,
the code compiles and works when only high priorty is setup

but when setup using high and low priority , it compiles fine , but the chip hangs it self
wonder if there was any changes to the includes

also the 18f47k40 have their own priorty interupt settings , wonder if these if set can be used




[/CODE]

[pedja089]

I'll just guess, but probably interrupt flag isn't reset in ISR.
So after exiting ISR, it will jump straight back into ISR.

[longpole001]

oki pedja ,thanks ill start isolating each of the isr see where it may not be rest correctly

[longpole001]

wondering if you played with the priority interupt system on the k40 it self for levels of each timer / etc as a way of not requiring the dt ints high / low priorty includes

' ------------------ Interupt Priority settings  ------------------------------ 
 ' Note: only services in use will show/ list the Interupt priorty setting 
 ' 1 = High Priority , 0 = Low Priority 
'    INTCON.5 = 0             ' Enable/ Disable priorty levels on interupts  ( default = 0)
      
'    IPR0.5 = 0               ' TMR0IP - Timer 0 POR = 1
'    IPR0.4 = 1               ' IOCIP  - IOC Interupt Priority  POR = 1 
    
    
'    IPR1.1 = 0               ' ADTIP  - ADC Threashold Interupt  POR = 0  
'    IPR1.0 = 0               ' ADIP   - ADC Interupt Priority  POR = 0    
       
'    IPR3.7 = 0               ' RC2IP  - usart2 RX Interupt Priority  POR = 0
'    IPR3.2 = 0               ' RC2IP  - usart2 TX Interupt Priority  POR = 0
    
'    IPR4.0 = 0               ' TMR1IF - Timer1 Overflow flag POR = 0 - timer 1 used for elapsed counter  ( set high priorty ?) 
'    IPR4.1 = 0               ' TMR2IF - Timer2 Overflow flag POR = 0 - timer 2 used for HWPWM - P10 dimmer control

[pedja089]

I didn't use K40. But it shouldn't be too hard to implement that.
As you have only one INT source. TMR2 INT should be disabled. As you need timer 2 only for PWM.

[tumbleweed]

wondering if you played with the priority interupt system on the k40 it self

Why would you do that? The file already takes care of that, and if you try and bypass it bad things will likely happen.

From the code block shown it looks like the only high-priority ISR you're using is the IOC.
Does your routine properly handle the steps required to clear the interrupt?
That's one of those that can't be cleared automatically since you have to clear the individual register/bit.

[longpole001]

yes had to place a reset interupt in each isr , when the isr is part of the low priorty,

the reset was not required in each isr when part of high priorty

thought the 18-int-k40 sorted it out when in low priorty as it did in high priorty /normal interupt handling
but it does not

[tumbleweed]

IOC is different from the other interrupts in that there are individual flags in the IOCxF registers that you have to clear manually.

The DT-INTs routine doesn't know which of these you're using, so you have to do it yourself.
It will try and clear the IOCIF bit in PIR0, but that bit is read-only so trying to clear that doesn't have any effect.

I don't think the interrupt priority setting has anything to do with this.

[longpole001]

the IOC had the reset done in it prior, as i have had issues with that on the 27k40
, but timer1, timer0,RX2 did not have any resets and were ok before they went to low priorty ISR

[tumbleweed]

That's odd... I don't see anything different about TMR0 or TMR1 in the file I have.

There's no point in trying to clear RCxIF... that bit is read-only and will be set as long as there's a character in the receive FIFO. The only way to clear it is to read RCxREG.