CONFIG issues with 18F26K22

[towlerg]

@Mike. No, just stand alone PK2cmd.exe and Pickit2v2.exe.

For what it's worth the config I use (in Proton but easily transposed)

	' internal clock 16MHz with 4xPLL = 64MHz
  $if _device = _18F26K22
  	Config_Start
  	  FOSC = INTIO67	   ; Internal oscillator block
  	  PLLCFG = On	       ; Oscillator multiplied by 4
  	  PRICLKEN = On	     ; Primary clock enabled
  	  FCMEN = OFF	       ; Fail-Safe Clock Monitor disabled
  	  IESO = OFF	       ; Oscillator Switchover mode disabled
  	  PWRTEN = On	       ; Power up timer enabled
  	  BOREN = On	       ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
  	  BORV = 285	       ; VBOR set to 2.85 V nominal
  	  WDTEN = OFF	       ; Watch dog timer is always disabled. SWDTEN has no effect.
  	  WDTPS = 32768	     ; 1:32768
  	  CCP2MX = PORTC1	   ; CCP2 input/output is multiplexed with RC1
  	  PBADEN = OFF	     ; PORTB<5:0> pins are configured as digital I/O on Reset
  	  CCP3MX = PORTB5	   ; P3A/CCP3 input/output is multiplexed with RB5
  	  HFOFST = On	       ; HFINTOSC output and ready status are not delayed by the oscillator stable status
  	  T3CMX = PORTC0	   ; T3CKI is on RC0
  	  P2BMX = PORTB5	   ; P2B is on RB5
  	  MCLRE = INTMCLR	   ; RE3 input pin enabled; MCLR disabled
  	  STVREN = On	       ; Stack full/underflow will cause Reset
  	  LVP = OFF	         ; Single-Supply ICSP disabled
  	  XINST = OFF	       ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
  	  Debug = OFF	       ; Disabled
  	  Cp0 = OFF	         ; Block 0 (000800-003FFFh) not code-protected
  	  CP1 = OFF	         ; Block 1 (004000-007FFFh) not code-protected
  	  CP2 = OFF	         ; Block 2 (008000-00BFFFh) not code-protected
  	  CP3 = OFF	         ; Block 3 (00C000-00FFFFh) not code-protected
  	  CPB = OFF	         ; Boot block (000000-0007FFh) not code-protected
  	  CPD = OFF	         ; Data EEPROM not code-protected
  	  WRT0 = OFF	       ; Block 0 (000800-003FFFh) not write-protected
  	  WRT1 = OFF	       ; Block 1 (004000-007FFFh) not write-protected
  	  WRT2 = OFF	       ; Block 2 (008000-00BFFFh) not write-protected
  	  WRT3 = OFF	       ; Block 3 (00C000-00FFFFh) not write-protected
  	  WRTC = OFF	       ; Configuration registers (300000-3000FFh) not write-protected
  	  WRTB = OFF	       ; Boot Block (000000-0007FFh) not write-protected
  	  WRTD = OFF	       ; Data EEPROM not write-protected
  	  EBTR0 = OFF	       ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
  	  EBTR1 = OFF	       ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
  	  EBTR2 = OFF	       ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
  	  EBTR3 = OFF	       ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
  	  EBTRB = OFF	       ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
  	Config_End
  $endif

[Dave]

MikeBZH, Here is the config I use for almost all of my 26K22 projects: 64Mhz internal OSC.

#CONFIG
;----- CONFIG1H Options --------------------------------------------------
__config _CONFIG1H, _FOSC_INTIO7_1H & _PLLCFG_ON_1H & _PRICLKEN_ON_1H & _FCMEN_ON_1H & _IESO_OFF_1H
;----- CONFIG2L Options --------------------------------------------------
__config _CONFIG2L, _PWRTEN_ON_2L & _BOREN_ON_2L & _BORV_190_2L
;----- CONFIG2H Options --------------------------------------------------
__config _CONFIG2H, _WDTEN_OFF_2H & _WDTPS_32768_2H
;----- CONFIG3H Options --------------------------------------------------
__config _CONFIG3H, _CCP2MX_PORTB3_3H & _PBADEN_OFF_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _MCLRE_EXTMCLR_3H
;----- CONFIG4L Options --------------------------------------------------
__config _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
#ENDCONFIG