This is a test.

    CONFIG FEXTOSC = OFF                ;External Oscillator not enabled
    CONFIG RSTOSC = HFINTOSC_64MHZ        ;HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1
    CONFIG CLKOUTEN = OFF                ;CLKOUT function is oFF
    CONFIG PR1WAY = OFF                    ;PRLOCK bit can be set and cleared repeatedly
    CONFIG CSWEN = ON                    ;Writing to NOSC and NDIV is allowed
    CONFIG FCMEN = OFF                    ;Fail-Safe Clock Monitor off
    CONFIG MCLRE = INTMCLR                ;If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR 
    CONFIG PWRTS = PWRT_OFF                ;PWRT set to off
    CONFIG MVECEN = OFF                    ;Interrupt contoller does NOT use vector table to prioritze interrupts
    CONFIG IVT1WAY = OFF                ;IVTLOCK bit can be cleared and set repeatedly
    CONFIG LPBOREN = OFF                ;ULPBOR disabled
    CONFIG BOREN = OFF                    ;Brown-out Reset enabled according to SBOREN
    CONFIG BORV = VBOR_245                ;Brown-out Reset Voltage (VBOR) set to 2.45V
    CONFIG ZCD = OFF                    ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
    CONFIG PPS1WAY = OFF                ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
    CONFIG STVREN = OFF                    ;Stack full/underflow will cause Reset
    CONFIG DEBUG = OFF                    ;Background debugger disabled
    CONFIG XINST = OFF                    ;Extended Instruction Set and Indexed Addressing Mode disabled
If this works I did something right.