One-Wire Timing Using PLL

[CocaColaKid]

Well I tried the caps thing and the same result. I then again tried the parasite power right on the board and it worked fine so that got me thinking about the 4.7k pull-up on the data line. I thought that maybe the resistance was a little too high so I tried a 2.2k and low and behold, it can to life. What I don't really understand though is why the difference when I switched between the 4 and 10 MHz crystals.

[mister_e]

Well all i can say, using the PLL the difference is 24MHZ. The problem would be the same with some I2C device at high SCL frequency. Some datasheet will suggest 1.8K for high frequency and 4.7K for lower frequency.