Pbp3.1.1

[mpgmike]

Vectored_INT.txt

Here is the code. I use an LCD to debug the values for DispVal. I'm using an external INT0 and TMR1 interrupts. Timer 1 overflows every 1 second. The Vector_Table_Init is mostly copy/paste from the Data Sheet. Labels T1ISR & INT0ISR are the Vectored Interrupts. The format deviates from the Data Sheet in that Address locations are denoted with "ORG 0x08C0" instead of "T1ISR CODE 0x08C0". I still don't understand why it has to use Non-Volitile Memory (NVM) for creating the Vector Addresses, but it works, and it's in the Data Sheet.

[richard]

thanks for that
out of curiosity in your lst file where does the pbp code start at ?
pbp 3.0
starts 000c

                   00136 ; Oscillator is 64MHz
                      01228   LIST
000000                01229     ORG RESET_ORG               ; Reset vector at 0
                      01238   LIST
000000 EF78 F000      01239         goto    INIT            ; Finish initialization
                      01249   LIST
000008                01250     ORG RESET_ORG + 8           ; High priority interrupt vector at 8
000008 EF7A F000      01251         goto    INTHAND         ; Goto high priority user interrupt handler
                      01487   LIST
00000C C00C FFE9      01488 ARRAYWRITE movff R5, FSR0L      ; Put the array pointer into FSR0     
000010 C00D FFEA      01489         movff   R5 + 1, FSR0H
000014 6EEE           01490         movwf   POSTINC0        ; Put the char into the array and bump up the address

[richard]

you might simplify the init seq to this, using labels to point to the isr vectors would be safer in the long term

ASM
Vector_Table_Init:
    MOVLW       0x00                        ;Vector Table Start Address: 00 4008h
    MOVWF       IVTBASEU, ACCESS
    MOVLW       0x40
    MOVWF       IVTBASEH, ACCESS
    MOVLW       0x08
    MOVWF       IVTBASEL, ACCESS
    
    MOVLW       0x00                        ;TMR1_INT = Vector #32
    MOVWF       TBLPTRU, ACCESS             ;4008h + [(32d) 20h * 2] = 4048
    MOVLW       0x40
    MOVWF       TBLPTRH, ACCESS
    MOVLW       0x48
    MOVWF       TBLPTRL, ACCESS
    
    MOVLW       0x30                        ;T1ISR >> 2; 08C0h >> 2 = 0230h
    MOVWF       TABLAT, ACCESS
    TBLWT*+
    MOVLW       0x02
    MOVWF       TABLAT, ACCESS
    TBLWT*+
    MOVLW       0x18
    MOVWF       TBLPTRL, ACCESS
    
    MOVLW       0x38                        ;INT0ISR >> 2; 08E0h >> 2 = 0238h
    MOVWF       TABLAT, ACCESS
    TBLWT*+
    MOVLW       0x02
    MOVWF       TABLAT, ACCESS
    TBLWT*+    
    BANKSEL     NVMCON1
    MOVLW       0x84                        ;Setting to write to PFM
    MOVWF       NVMCON1
    MOVLW       0x55                        ;Required unlock sequence
    MOVWF       NVMCON2
    MOVLW       0xAA
    MOVWF       NVMCON2
    BSF         NVMCON1, WR                 ;Start writing to PFM
    BTFSC       NVMCON1, WR                 ;Wait for write to complete
    GOTO        $-2    
    RETURN      1
ENDASM

caveat what is the label size for pbp3.1 ? might limit location to first 64k block

[richard]

using labels

isr

T1ISR:
ASM                                  ;ISR code  relocateable
    BANKSEL PIR4                        ;BANKSELECT for PIR4
    BCF PIR4,0                          ;Clear TMR1IF
;    BANKSEL LATC                        ;BANKSELECT for LATC
;    BTG _LED                            ;Bit Toggle LATC.3 (LED)
    MOVLW 086h
    BANKSEL TMR1H                       ;BANKSELECT for TMR1
    MOVWF TMR1H, 1
;    TMR1H = $86
    MOVLW 0E7h                          ;34535d = 1 Second Interrupts
    MOVWF TMR1L, 1
;    TMR1L = $E7
    BANKSEL T1CON                       ;BANKSELECT for T1CON
    MOVLW 1                             ;T1CON = %00000001
    MOVWF T1CON, 1
;    T1CON = %00000001
    MOVLB 0
    BSF Cycle
    INFSNZ DispL
    INCF DispH
    RETFIE FAST                         ;RETURN & Restore
ENDASM

in init

  
    MOVLW       low (_T1ISR >> 2) ; 08C0h >> 2 = 0230h
    MOVWF       TABLAT, ACCESS
    TBLWT*+
    MOVLW       high (_T1ISR >> 2)
    MOVWF       TABLAT, ACCESS
    TBLWT*+

caveat what is the label size for pbp3.1 ? might limit location to first 64k block

[tumbleweed]

The format deviates from the Data Sheet in that Address locations are denoted with "ORG 0x08C0" instead of "T1ISR CODE 0x08C0". I still don't understand why it has to use Non-Volitile Memory (NVM) for creating the Vector Addresses, but it works

The difference between ORG and CODE is that you use ORG when working with the assembler in absolute mode, and CODE when using the assembler in relocatable mode (ie using a linker). PBP works in absolute mode, so use ORG.

The NVM instructions are to set the table of vectors (IVT) into the program flash memory. The IVTBASE registers set where the table starts in memory but you still have to put the address of each interrupt handler into the IVT table.

[mpgmike]

Thanks Tumbleweed. As to the other questions & comments, I don't know where to find those answers; "what is the label size for PBP3.1?"

Richard, you seem to indicate you are using PBP 3.0 (?). I let the linker set the PBP start address. I didn't open the List file to find out. Since I'm just copying from Data Sheets, it would be nice if someone with PBP 3.1 could test some of the mentioned short cuts to see if they work. If they do, I'll try to figure out what was actually done and learn from it.

[richard]

I wonder if there is any gain using vectored interrupts , for all the extra effort and the risk in locating the vector table inappropriately {like slap bang in the middle of your pgm space}. I cant see that it will perform significantly better than a normal preemptive isr routine for multiple interrupt sources .
I asked about the pbp reset org thinking it would be nice to locate the ivt at that point and then use "define RESET ORG" to skip over it .
you could then load your vectors at compile time with @ dw ...... . heaps easier to manage . still need to Vector Table Start Address regs though.
I have some chips on order with element14 but the have none in stock , when the arrive I will try with xc8 to see if its worth the effort.
I wonder why they [microchip] did not just allocate more vector address permanently like an avr chip
"what is the label size for PBP3.1?" since there are 128k chips in this family I guess they have to at least big enough , still test it first