How to verify HS_PLL clock speed

[CocaColaKid]

Would this not enable the x4 PLL?

@ __CONFIG _CONFIG1H, _OSCS_OFF_1H & _HSPLL_OSC_1H
@ __CONFIG _CONFIG2L, _BOR_ON_2L & _PWRT_ON_2L & _BORV_45_2L
@ __CONFIG _CONFIG2H, _WDT_ON_2H 
@ __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L

[Bruce]

It should, but check this with your programmer before programing that part.

Also, you might want to use the osc resistor shown in the datasheet since this may be over driving your crystal. HS uses a higher drive output on OSC2.

[CocaColaKid]

I'm actually using a TTL oscillator so this shouldn't be an issues should it?

[Bruce]

"EDIT"

For OSC2 to output clock/4 with a TTL clock oscillator, you'll need to use EC or ECIO mode.

HSPLL isn't available for EC or ECIO mode. With a 4MHz TTL clock oscillator, you'll have only 4MHz. HSPLL mode works with the TTL clock if you set config fuses for HSPLL, but you can't use the OSC2 pin in HS mode. Only EC or ECIO modes.

[CocaColaKid]

ah, I'll drop in a crystal then, I have both at my disposable.

[Bruce]

You know, it's not really 100% clear from the datasheet, but looking at Figure 2-2, it does appear an external clock, I.E. a TTL osc can be input to OSC1, and you can select HS, XT or LP modes, so it "appears" you can use a TTL clock in on OSC1, and still make use of the HSPLL as long as you have HS set in config.

I'll have to experiment with that one.

[Darrel Taylor]

Just wanted to add that the PLL only starts up properly on Power-Up.

The first time you program a chip with the PLL turned on, it won't actually start working at x4 untill you turn the power off and on again. A simple reset of MCLR wont do it.

<br>