Several assumptions on my part. Your code actually looked fine except where you initially used the high & low commands in the setpotszero sub.

Setting port latches followed by tris in the beginning reduces the possibility of read-modify-write when initializing both pots in the setpotszero routine. Using high & low together like that with the port latches in random states will normally cause headaches.

Why high RC0 created the pulse on RC1..? The only thing I could see (short of capacitive coupling) that may cause this was using the high & low commands so close together.

With low rst1 immediately followed by high rst2 it seemed to be showing high on RC1 before RC0 had settled.

Dropping the short delay in there just allows the RC0 logic to settle back to 0 before RC1 is taken high. Successive operations on a port, pin-by-pin, can cause odd things to happen depending on the load on each pin. So the brief delay sometimes helps.

Just a guess, but I'm glad it worked for you.

Once in a while I get someting right....;o}