Programming RFM radio modules in Basic

[astanapane]

Now a small step, in the code is to add the DIO0 pin from RFM69HCW to PIC18F26K22.

As i read from the net, that pin is the:

Received data ready interrupt signal from RFM69HCW to microcontroller

TRIS register must also be configured as input at that pin i guess as the RFM69HCW is the one sending data to PIC.

That i believe will complete the connections between the PIC and the RFM.

'**********************************************************************
'*  Name    : 18F26K22.BAS                                            *
'*  Author  : [Leonardo Bilalis]                                      *
'*  Notice  : Copyright (c) 2018 [Leonardo Bilalis]                   *
'*          : All Rights Reserved                                     *
'*  Date    : 30/Jun/2018                                             *
'*  Version : 1.0                                                     *
'*  Notes   : This is a GPS Tracker based on the following components *
'*          : PIC18F26K22 or PIC18F46K22 @ 64Mhz                      *
'*          : MKT 3333 or 3339 GPS MODULE                             *
'*          : 4D Systems ULCD Goldelox or Picasso Graphic Processor   *
'*          : RFM69HCW the range will be approximatelly 1000 meters   *
'**********************************************************************     

  #CONFIG   ;
     CONFIG FOSC     = HSHP	        ; HS oscillator (high power > 16 MHz)
    CONFIG PLLCFG    = ON	        ;Oscillator multiplied by 4  
    CONFIG PRICLKEN  = ON	        ;Primary clock enabled
    CONFIG FCMEN     = OFF	        ;Fail-Safe Clock Monitor disabled
    CONFIG IESO      = OFF	        ;Oscillator Switchover mode disabled
    CONFIG  BOREN    = SBORDIS      ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
    CONFIG  WDTEN    = ON           ; WDT is always enabled. SWDTEN bit has no effect                     ;|
    CONFIG  WDTPS    = 32768        ; 1:32768 ---> HERE enable the watchdog timer with a 1:32768 postscale;|
    CONFIG  PWRTEN   = ON
    CONFIG  HFOFST   = ON           ; HFINTOSC output and ready status are not delayed by the oscillator stable status
    CONFIG  MCLRE    = EXTMCLR      ; MCLR pin enabled, RE3 input pin disabled
    CONFIG  LVP      = OFF          ; Single-Supply ICSP disabled
    CONFIG  XINST    = OFF          ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    CONFIG  DEBUG    = OFF          ; Disabled  
    CONFIG  CP0 = OFF             ; Block 0 (000800-003FFFh) not code-protected
    CONFIG  CP1 = OFF             ; Block 1 (004000-007FFFh) not code-protected
    CONFIG  CP2 = OFF             ; Block 2 (008000-00BFFFh) not code-protected
    CONFIG  CP3 = OFF             ; Block 3 (00C000-00FFFFh) not code-protected
    CONFIG  CPB = OFF             ; Boot block (000000-0007FFh) not code-protected
    CONFIG  CPD = OFF             ; Data EEPROM not code-protected
    CONFIG  WRT0 = OFF            ; Block 0 (000800-003FFFh) not write-protected
    CONFIG  WRT1 = OFF            ; Block 1 (004000-007FFFh) not write-protected
    CONFIG  WRT2 = OFF            ; Block 2 (008000-00BFFFh) not write-protected
    CONFIG  WRT3 = OFF            ; Block 3 (00C000-00FFFFh) not write-protected
    CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) not write-protected
    CONFIG  WRTB = OFF            ; Boot Block (000000-0007FFh) not write-protected
    CONFIG  WRTD = OFF            ; Data EEPROM not write-protected
    CONFIG  EBTR0 = OFF           ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
    CONFIG  EBTR1 = OFF           ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
    CONFIG  EBTR2 = OFF           ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
    CONFIG  EBTR3 = OFF           ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
    CONFIG  EBTRB = OFF           ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
  #ENDCONFIG
  
define  OSC 64
        
OSCCON    = %01110000   ; 64Mhz
OSCTUNE.6 = 1           ; Enable 4x PLL
while ! osccon2.7 :WEND ; to make sure the pll has stabilised before you run any other code


initialize:
CLEAR                   

TRISA = %11011111 
TRISC = %11010111  



SSPCON1 = %00100010 ' in here we se the 5th bit of the SSPCON1 register and the last 4 bits for the clock speed at 64Mhz.
SSP1STAT = %11000000  ' in here i need a help to understand what bits must be configured



CS1      VAR           LATA.5  ' chip select (SS) from PIC18F26K22 to RFM69HCW
DIO0     VAR           PORTC.2 ' Received data ready interrupt signal from RFM69HCW to microcontroller
SCK1     VAR           PORTC.3 ' clock from PIC18F26K22 to RFM69HCW
SDI1     VAR           PORTC.4 ' data IN , MISO from PIC18F26K22 to RFM69HCW
SDO1     VAR           PORTC.5 ' data OUT, MOSI from PIC18F26K22 to RFM69HCW

SSPIF   VAR     PIR1.3          ' SPI interrupt flag
SMP     VAR     SSP1STAT.7      ' Data input sample phase
CKE     VAR     SSP1STAT.6      ' Clock Edge Select bit
SSPEN   VAR     SSP1CON1.5      ' SSP Enable bit
CKP     VAR     SSP1CON1.4      ' Clock Polarity Select

CS1    = 1