Ok that i will set, but still i do not understand "SPI Clock Edge Select bit" does inside the code?

Does it gives the "OK" when it is "1" Transmit occurs on transition from active to Idle clock state

which means that the data transmitted on the falling edge of SCK?
yes the tx data is valid on sck's falling edge

is a particularly dangerous idea when dealing with devices that have a chip select low input Ok i will fix this. Do you mention this state, because it is accidentally dangerous to apply 5V on the circuit?
no , its because a device with a cs low type input will assert its outputs when cs is low, they should not be asserted until every thing is in order, imagine if you had mutpile devices on the spi bus.

I have a step up/ step down regulator 1.2A at 3.3 volts for both of the test boards. I hope this will eliminate the issue.
it wont

Many people like me cannot understand clearly the difference between the LAT and PORT

its quite simple , at high clock speeds rmw issues abound if you don't use lat regs for bit outputs
http://www.microchip.com/webinars.mi...cName=en556253