It's only doing a simple repetitive task - triggered on dig ip by comparators, dig ops driving at any one time one of several hard pull-up transistors in a multiple 1-wire master circuit, with retrigger (blocking) timers. It's basically doing something that could be handled quicker by a few logic gates. The 1-wire communication proper (and everything else) is handled by another on-board µC - of the 18F family.
So the 16F1782 is not writing to EEPROM etc. I'll leave that interesting experiment @80MHz to someone else!