MikroE clicker, 18f47J53, serout 2 to serial LCD issues

[alec]

Thanks Henrik
The default config file has the PLL disabled. I did get it running on the internal oscillator, so yes, its a configuration issue. More time with the datasheet I guess...

[alec]

And yes, I'm using the bootloader.

Thanks much - I'll keep reading the datasheet, see what I'm missing.

Take care

Alec

[HenrikOlsson]

Hi,
If you're using the MikroE USB bootloader then the device is running at 48MHz, not 16MHz so you need to change your DEFINE OSC 16 to DEFINE OSC 48 - try it!

And here's the default PBP configuration from my PBP3 installation:

;  The PBP default configuration for the PIC18F47J53 is:
;
;  #CONFIG
;    CONFIG  WDTEN = ON            ; Enabled
;    CONFIG  PLLDIV = 5            ; Divide by 5 (20 MHz oscillator input)
;    CONFIG  CFGPLLEN = OFF        ; PLL Disabled
;    CONFIG  STVREN = ON           ; Enabled
;    CONFIG  XINST = OFF           ; Disabled
;    CONFIG  CPUDIV = OSC1         ; No CPU system clock divide
;    CONFIG  CP0 = OFF             ; Program memory is not code-protected
;    CONFIG  OSC = HSPLL           ; HS+PLL, USB-HS+PLL
;    CONFIG  SOSCSEL = HIGH        ; High Power T1OSC/SOSC circuit selected
;    CONFIG  CLKOEC = ON           ; CLKO output enabled on the RA6 pin
;    CONFIG  FCMEN = OFF           ; Disabled
;    CONFIG  IESO = OFF            ; Disabled
;    CONFIG  WDTPS = 512           ; 1:512
;    CONFIG  DSWDTOSC = INTOSCREF  ; DSWDT uses INTRC
;    CONFIG  RTCOSC = T1OSCREF     ; RTCC uses T1OSC/T1CKI
;    CONFIG  DSBOREN = ON          ; Enabled
;    CONFIG  DSWDTEN = ON          ; Enabled
;    CONFIG  DSWDTPS = G2          ; 1:2,147,483,648 (25.7 days)
;    CONFIG  IOL1WAY = ON          ; The IOLOCK bit (PPSCON<0>) can be set once
;    CONFIG  ADCSEL = BIT12        ; 12 - Bit ADC Enabled
;    CONFIG  MSSP7B_EN = MSK7      ; 7 Bit address masking mode
;    CONFIG  WPFP = PAGE_0         ; Write Protect Program Flash Page 0
;    CONFIG  WPCFG = OFF           ; Configuration Words page not erase/write-protected
;    CONFIG  WPDIS = OFF           ; WPFP<6:0>/WPEND region ignored
;    CONFIG  WPEND = PAGE_WPFP     ; Pages WPFP<6:0> through Configuration Words erase/write protected
;    CONFIG  LS48MHZ = SYS24X4     ; System clock at 24 MHz USB CLKEN divide-by is set to 4
;  #ENDCONFIG

Look at the lines in bold. The PLL is enabled with a division ratio of 5. The MicroE Clicker board has a 16MHz x-tal which will result in an input frequency to the PLL of 16/5=3.2MHz where it expects to get 4MHz, the output will be 38.4MHz instead of the expected 48MHz. So even if the bootloader DOES write the CONFIG bits using the PBP default ones for that board doesn't work.

/Henrik.

[alec]

OK Henrik - you were right. I changed PLLDIV to 4, and set OSC = 48, and it works.

But now I have to ask why it didn't work when I tried OSC = HS

; CONFIG CFGPLLEN = OFF ; PLL Disabled - doesn't this mean PLL is turned off?

Thanks for your help - as usual more to learn.

Thanks again

Alec

[HenrikOlsson]

Hi,
OK, I'll try this again:
When you're using the MikroE USB HID bootloader the CONFIG bits aren't written to device since doing so can make the bootloader it self stop working, basically bricking the board. The bootloader code (and the actual USB hardware in the PIC) relies on the fact that the PIC is running at 48MHz. IF the bootloader allowed itself to change the CONFIG it would sort of allow itself to commit suicide and you'd need to reload the bootloader into the chip using a normal device programmer. I'm 99.9% sure this is the case with the MikroE USB Bootloader as well.

This means that you changing to OSC = HS or trying to change the PLLDIV doesn't actually do anything to the operation of the device. It is and always has been running at 48MHz. I only said that IF the config bits where updated the default PBP config, with PLLDIV=5 isn't correct when using a 16MHz x-tal. But for that change to actually end up in the chip you'd need to use an actual device programmer.

I'm pretty sure that the sole thing that made it work in your case was specifying the correct oscillator frequency to the compiler, ie DEFINE OSC 48.

CONFIG CFGPLLEN = OFF ; PLL Disabled - doesn't this mean PLL is turned off?

Yes, you're quite right. It means that the PLL is off by default but that it CAN - (because OSC = HSPLL) - be turned ON at runtime by setting OSCTUNE.6
If CFGPLLEN = ON then the PLL is permanently on and can not be turned off by software.

Does that make any sort of sense?

/Henrik.

[alec]

Thanks Henrik, now it makes sense. When I got it to operate correctly under the internal oscillator, by setting the correct values for the OSCCON register, telling it to use the 8 mhz internal clock, it works because software changed the clock source, and not from setting the configuration files which the bootloader ignores to make sure that the configuration needed for the bootloader never changes.

Thanks again

Alec