MCP41xxx Digital pot issue

[jmgelba]

I cant seem to get a MCP41100 single digital pot to work. The wiper is always at mid point. I've tried many different things to get this working but just no luck. Can anyone see what the issue might be? There's data out to the pot and timings seem fine so I have no idea what is going wrong at this point.

On a second look - it seems the SCK pin is going high at the start of data and then low after the 16 bits have been sent. Shouldn't it go high and low for each bit sent?

Define OSC 48
Define	ADC_BITS	  10	' Set number of bits in result
Define	ADC_CLOCK	   3	' Set clock source (3=rc)
Define	ADC_SAMPLEUS  50	' Set sampling time in uS
Include "modedefs.bas"
SCK     var     PORTB.1     ' Alias PORTC.3 to SCK (serial data clock)
SDO     var     PORTA.5     ' Alias PORTC.5 to SDO (serial data out)
CS      var     PORTB.2     ' Alias PORTC.2 to C_EN (chip enable)
POT0    var     byte        ' 
increment var byte
increment = 0

TRISA = %11011111	' Set PORTA to all input except 5
   ADCON1 = %00000000	' Set PORTA analog and right justify result
   ADCON2.7=1
TRISB = %00011001
TRISC = %01000000

        HIGH    CS                  'Chip enable high to start
        high    sck                 'Mode 1,1 SCK idles high

loop1
increment = increment + 1 
write 0, increment

pot0 = %00010001
       
GOSUB   write_pots
goto loop1       
      
WRITE_POTS:                                 

        low     CS                          ' Make chip active
        shiftout    sdo,sck,5,[pot0,increment]     ' Mode 1,1 / Mode 5 PBP - clock idles high, MSB shift out first
        high    CS                          ' 
        
return

End