A/D Conversion Clock Select bits confussion ..

[aratti]

You cannot use the full function because it is foundamentally a logaritmic function. For the ADC convertion you need a linear function. Once time, resistence and capacity are fixed than the charging function depend only from the voltage applied. If during the charging time you do not pass the 1T point of the function, than the charging function can be considered "quasi liner" and the system work. In other words you can deduce the value of the voltage applied. If you pass the 1T point then thing become more complicated since from that point on the function is purely logaritmic.

Cheers
Al.

[tumbleweed]

You're somehow mixing Acquisition time with the linearity of the ADC conversion function.

For the Acquisition time, you need the sample cap to charge to whatever value you want the ADC to convert. Period.

The time constant of an RC network is T=RC, and after one T the voltage across the cap is roughly 66% of the input voltage.
If you look at T vs percent, you get:

1    63.2% 
2    86.5% 
3    95.0% 
4    98.2% 
5    99.3% 
10   99.995%
20   99.9999998%

If you set the Acquisition time to 1T and then convert the value, you could be VERY wrong... 37% wrong. Of course, that depends on the new input voltage you want to convert and any existing charge on the sample cap, but T gives you a worst-case number.

For example, an 8-bit ADC (1 part in 256, or 0.39%) would need an acquisition time of better than 5T, but there's nothing wrong with giving it 10T or 20T or 100T, as long as nothing else changes in that time.

You do not have to hit some magic 1T window trying to get it into a "quasi-linear" range, or guess at things to "see if it's good enough".

[aratti]

No much to say, just keep your convintions if you are happy with them.

Al.

[HenrikOlsson]

Hi,
I must say I'm quite confused and intruiged by this statement as well.

As I'm currently messing around with the ADC in the 18F2431 I've been reading up on the acquisition time and conversion time requirement(s) in order to better understand it and I can't for the life of me find any references to issues with too long acqusition time.

The datasheet is pretty clear on the point that the conversion clock period (TAD) needs to be as short as possible, yet still longer than the minimum (418ns for 18F2431). This means that when operating at 40MHz the selection FOsc/32 must be used since that gives a TAD of 800ns. Going a step lower (FOsc/16) would violate the 416ns requirement. A conversion takes 12TAD so 9.6us in this case.

The minimum acqusition time, ie for how long the S/H capacitor is connected to the analog input before the conversion starts dependes on the source impedence driving the inputs, temperature range etc. For a 1k source impedence I calculated the minimum acquistion time to 2.38us which is ~3TAD in my case. I'm well below 1k in source impedence but I'm going to stick with a acqusition time of 4TAD.

This gives me a total A to D time of 3.2+9.6=12.8us.

Nowhere can I see any reference to issues with too long acqusition time.

Confused.....

/Henrik.

[richard]

if it were possible that the acquisition time could be too long then surely the optimum acquisition time would have to varied logarithmically according to the instantaneous sample voltage . the suggestion is not realistic ,unsubstantiated and unworkable

[tumbleweed]

Agreed.

Confused...

Don't be. You have it correct.

What you're computing is the minimum time it takes for the RC sample/hold network to charge to the input voltage assuming you're making a full-scale voltage change. Depending on the accuracy you're trying to reach that normally takes about 7T-8T. Once it's charged up (or down), you're good to go, but it does no harm in waiting longer (as long as nothing else changes).

The only thing to watch out for is if you change PIC's be sure to check the specs of the new device. The source resistance of the internal switch and the cap can be different for different families, so that can change the calculation.

[aratti]

Henrik, I am using a rather old pic (18F2620), I still have a couple of hundreds of them. But timing apart your and mine are very similar in the setting of the TAD value and the acquisition time.
As far as TAD value is concerned I can Select value up to Fosc/64 (minimum delay required for 1 TAD = 1.6 us)
As far as ACQUISTION TIME is concerned, I have a range selectable from 2 TAD to 20 TAD. (So you have a lower and upper limits)

I made some experimenting some years ago, using the manual acquisition time, so I could increase/decrease the acquisition time beyond the 2/20 TAD limits. Unfortunatly I was not able to find these data (I have been digging for the whole day without success) but I assure you they were very interesting. The experiment was done taking 100 reading at three specific points of the 10 bits range. First point was fixed to 10 ADC count (low end), second point in the middle at 512 ADC count and the third point at 1012 ADC count (high end). These reading were taken at different acquisition time going from 1 us up to 200 us in steps of 10 us each.
Once, all the data were collected ( they have been collected via RS232 connection and loaded directly into an Excel sheet), the statistic applied were : Average/Standard deviation/standard error.
Looking at the standard error, I noticed an increase in the two extreme regions when the acquisition time was too low or higher than the 2/20 TADs region , no significant variation of standard error were observed in the middle range.
I will continue to search these files (I am sure I still have them somewhere) and If I found them I will post them here in this thread.
But everybody, with some time to spare, can repeat the experiment on his own.
Cheers.
Al