Should we not calculate it 1.6x11 Tad = 17.6 uS ? Thus is it not better to set it to 20 uS ?
Should we not calculate it 1.6x11 Tad = 17.6 uS ? Thus is it not better to set it to 20 uS ?
The 11 TADs is the time taken by the MCU for the 10 bits convertion! Please do not confuse acquisition with convertion. The setting suggested is the time you will give to the sample & hold capacitor to charge with your input dc value. This time should be enough to charge the cap not beyond the 1T, because beyond this point the charging function is no longer quasi-linear, but totaly logaritmic.
You can set it to 20 us and see If your ADC reading are consistent and adjust this value to suite your need. (Remember that the best acquisition time will depend by the hardware setting, so every circuit has his own best acquisition time)
Cheers
Al.
Last edited by aratti; - 20th July 2015 at 12:22.
All progress began with an idea
Grazie tante per la risposta cara aratti ..![]()
I remember saving a link to this... http://www.edaboard.com/nextoldesttoentry1570.html
page. Be sure to hit the "next" button at the bottom of the page where there is discussion of acquisition time.
hope this helps you.
Dwight
These PIC's are like intricate puzzles just waiting for one to discover their secrets and MASTER their capabilities.
I remember saving a link to this... http://www.edaboard.com/nextoldesttoentry1570.html
page. Be sure to hit the "next" button at the bottom of the page to go to Part 2 where there is discussion of acquisition time.
Possibly something of value there.
Last edited by Heckler; - 21st July 2015 at 05:13.
Dwight
These PIC's are like intricate puzzles just waiting for one to discover their secrets and MASTER their capabilities.
The only part I cant understand is the line he somehow calculated 40 + 38.4 us = 78.4 uS .. where did that 40 come from ?
40 us is the value the author arbitrarely gives as acquisition time "sampleus parameter".
Remember:
A too high acquisition time will give issues when the analog input approch the V(ref+)
A too low acquisition time will give issues when the analog input approch the zero
So, if you do not see any issues in your reading at the extreme of the reading field then the acquisition time used is correct!
Ciao, complimenti per il tuo italiano!
Al.
Last edited by aratti; - 21st July 2015 at 14:37.
All progress began with an idea
Where do you get this from?A too high acquisition time will give issues when the analog input approch the V(ref+)
A too low acquisition time will give issues when the analog input approch the zero
The aquisition time is the MINIMUM amount of time you have to wait for the holding capacitor (and it's RC network) to fully charge/discharge to the voltage level you're sampling.
If you set the acquisition time too low then you won't have allowed enough time for the charge on the capacitor to reach the desired level, and you'll get an incorrect conversion. It doesn't matter so much if the input is near Vref or zero, it'll be wrong.
If you're measuring a DC voltage, there is no "too high" an aquisition time.
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