A/D Conversion Clock Select bits confussion ..


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    Default Re: A/D Conversion Clock Select bits confussion ..

    The sampleus parameter is the time given for the acquisition ( changing the sample & hold capacitor). This timing is critical since you must charge the capacitor no more than 1T..(up to 1T the charging curve is quasi linear) Now If you have decided to use fosc = 16 MHz than the minimum pauseus you can get is 5 us so a Define adc_sampleus 15 should give you good results.

    Cheers

    Al.
    Last edited by aratti; - 20th July 2015 at 09:02.
    All progress began with an idea

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