Hi,
I must say I'm quite confused and intruiged by this statement as well.

As I'm currently messing around with the ADC in the 18F2431 I've been reading up on the acquisition time and conversion time requirement(s) in order to better understand it and I can't for the life of me find any references to issues with too long acqusition time.

The datasheet is pretty clear on the point that the conversion clock period (TAD) needs to be as short as possible, yet still longer than the minimum (418ns for 18F2431). This means that when operating at 40MHz the selection FOsc/32 must be used since that gives a TAD of 800ns. Going a step lower (FOsc/16) would violate the 416ns requirement. A conversion takes 12TAD so 9.6us in this case.

The minimum acqusition time, ie for how long the S/H capacitor is connected to the analog input before the conversion starts dependes on the source impedence driving the inputs, temperature range etc. For a 1k source impedence I calculated the minimum acquistion time to 2.38us which is ~3TAD in my case. I'm well below 1k in source impedence but I'm going to stick with a acqusition time of 4TAD.

This gives me a total A to D time of 3.2+9.6=12.8us.

Nowhere can I see any reference to issues with too long acqusition time.

Confused.....

/Henrik.